---------- Begin Simulation Statistics ---------- final_tick 1240635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 103827 # Simulator instruction rate (inst/s) host_mem_usage 818408 # Number of bytes of host memory used host_op_rate 118701 # Simulator op (including micro ops) rate (op/s) host_seconds 6.95 # Real time elapsed on the host host_tick_rate 178541152 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 721443 # Number of instructions simulated sim_ops 824818 # Number of ops (including micro ops) simulated sim_seconds 0.001241 # Number of seconds simulated sim_ticks 1240635000 # Number of ticks simulated system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 99.680876 # BTB Hit Percentage system.cpu.branchPred.BTBHits 103078 # Number of BTB hits system.cpu.branchPred.BTBLookups 103408 # Number of BTB lookups system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.branchPred.condIncorrect 715 # Number of conditional branches incorrect system.cpu.branchPred.condPredicted 104603 # Number of conditional branches predicted system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu.branchPred.indirectLookups 74 # Number of indirect predictor lookups. system.cpu.branchPred.indirectMisses 74 # Number of indirect misses. system.cpu.branchPred.lookups 105375 # Number of BP lookups system.cpu.branchPred.usedRAS 266 # Number of times the RAS was used to get a target. system.cpu.branchPredindirectMispredicted 34 # Number of mispredicted indirect branches. system.cpu.cc_regfile_reads 309135 # number of cc regfile reads system.cpu.cc_regfile_writes 309099 # number of cc regfile writes system.cpu.commit.amos 0 # Number of atomic instructions committed system.cpu.commit.branchMispredicts 564 # The number of times a branch was mispredicted system.cpu.commit.branches 103571 # Number of branches committed system.cpu.commit.bw_lim_events 753 # number cycles where commit BW limit reached system.cpu.commit.commitNonSpecStalls 22 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 2279 # The number of squashed insts skipped by commit system.cpu.commit.committedInsts 721460 # Number of instructions committed system.cpu.commit.committedOps 824835 # Number of ops (including micro ops) committed system.cpu.commit.committed_per_cycle::samples 2459157 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.335414 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 0.906805 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 2048703 83.31% 83.31% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 204943 8.33% 91.64% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 102514 4.17% 95.81% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 387 0.02% 95.83% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 101673 4.13% 99.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 134 0.01% 99.97% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 33 0.00% 99.97% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 17 0.00% 99.97% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 753 0.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 2459157 # Number of insts commited each cycle system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.function_calls 111 # Number of function calls committed. system.cpu.commit.int_insts 415223 # Number of committed integer instructions. system.cpu.commit.loads 103115 # Number of loads committed system.cpu.commit.membars 14 # Number of memory barriers committed system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 311785 37.80% 37.80% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 3 0.00% 37.80% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 2 0.00% 37.80% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 204400 24.78% 62.58% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.58% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.58% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.58% # Class of committed instruction system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 62.58% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 102200 12.39% 74.97% # Class of committed instruction system.cpu.commit.op_class_0::FloatMisc 1 0.00% 74.97% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 74.97% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 11 0.00% 74.97% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 74.97% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 8 0.00% 74.97% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 8 0.00% 74.97% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 74.97% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 8 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdDiv 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdAes 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 74.98% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 103115 12.50% 87.48% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 103292 12.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 824835 # Class of committed instruction system.cpu.commit.refs 206407 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.vec_insts 511182 # Number of committed Vector instructions. system.cpu.committedInsts 721443 # Number of Instructions Simulated system.cpu.committedOps 824818 # Number of Ops (including micro ops) Simulated system.cpu.cpi 3.439317 # CPI: Cycles Per Instruction system.cpu.cpi_total 3.439317 # CPI: Total CPI of All Threads system.cpu.decode.BlockedCycles 2033585 # Number of cycles decode is blocked system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction system.cpu.decode.BranchResolved 102704 # Number of times decode resolved a branch system.cpu.decode.DecodedInsts 829347 # Number of instructions handled by decode system.cpu.decode.IdleCycles 147032 # Number of cycles decode is idle system.cpu.decode.RunCycles 42260 # Number of cycles decode is running system.cpu.decode.SquashCycles 574 # Number of cycles decode is squashing system.cpu.decode.SquashedInsts 1260 # Number of squashed instructions handled by decode system.cpu.decode.UnblockCycles 236394 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 105375 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 312101 # Number of cache lines fetched system.cpu.fetch.Cycles 2137729 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 343 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 731037 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 1450 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.042468 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 321391 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 103344 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.294622 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 2459845 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.339764 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 0.789675 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 2008959 81.67% 81.67% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 172185 7.00% 88.67% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 172521 7.01% 95.68% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 106180 4.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 2459845 # Number of instructions fetched each cycle (Total) system.cpu.idleCycles 21426 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.branchMispredicts 600 # Number of branch mispredicts detected at execute system.cpu.iew.exec_branches 103843 # Number of branches executed system.cpu.iew.exec_nop 35 # number of nop insts executed system.cpu.iew.exec_rate 0.333093 # Inst execution rate system.cpu.iew.exec_refs 206850 # number of memory reference insts executed system.cpu.iew.exec_stores 103408 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 114 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 103635 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 103569 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 827645 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 103442 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 436 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 826494 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 93 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 574 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 92 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.squashedLoads 520 # Number of loads squashed system.cpu.iew.lsq.thread0.squashedStores 277 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 495 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly system.cpu.iew.wb_consumers 522857 # num instructions consuming a value system.cpu.iew.wb_count 826241 # cumulative count of insts written-back system.cpu.iew.wb_fanout 0.792354 # average fanout of values written-back system.cpu.iew.wb_producers 414288 # num instructions producing a value system.cpu.iew.wb_rate 0.332991 # insts written-back per cycle system.cpu.iew.wb_sent 826314 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 520659 # number of integer regfile reads system.cpu.int_regfile_writes 210421 # number of integer regfile writes system.cpu.ipc 0.290755 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.290755 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 313257 37.88% 37.88% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 3 0.00% 37.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 2 0.00% 37.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 204400 24.72% 62.60% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.60% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 102200 12.36% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 11 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 8 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 8 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 8 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdAes 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 74.96% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 103579 12.53% 87.49% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 103451 12.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 826930 # Type of FU issued system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fu_busy_cnt 1343 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001624 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 461 34.33% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMisc 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.33% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 2 0.15% 34.48% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 2 0.15% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdDiv 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAes 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAesMix 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 34.62% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 357 26.58% 61.21% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 521 38.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 316949 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 3092621 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 315059 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_writes 318990 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 827580 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 826930 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 2791 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 1969 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.issued_per_cycle::samples 2459845 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.336172 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.581689 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 1773835 72.11% 72.11% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 545841 22.19% 94.30% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 139436 5.67% 99.97% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 715 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 18 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 2459845 # Number of insts issued each cycle system.cpu.iq.rate 0.333269 # Inst issue rate system.cpu.iq.vec_alu_accesses 511322 # Number of vector alu accesses system.cpu.iq.vec_inst_queue_reads 1022509 # Number of vector instruction queue reads system.cpu.iq.vec_inst_queue_wakeup_accesses 511182 # Number of vector instruction queue wakeup accesses system.cpu.iq.vec_inst_queue_writes 511414 # Number of vector instruction queue writes system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 103635 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 103569 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 3083091 # number of misc regfile reads system.cpu.misc_regfile_writes 306657 # number of misc regfile writes system.cpu.numCycles 2481271 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.BlockCycles 1691366 # Number of cycles rename is blocking system.cpu.rename.CommittedMaps 1233722 # Number of HB maps that are committed system.cpu.rename.IdleCycles 215481 # Number of cycles rename is idle system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.ROBFullEvents 304166 # Number of times rename has blocked due to ROB full system.cpu.rename.RenameLookups 2877119 # Number of register rename lookups that rename has made system.cpu.rename.RenamedInsts 828108 # Number of instructions processed by rename system.cpu.rename.RenamedOperands 1237061 # Number of destination operands rename has renamed system.cpu.rename.RunCycles 176011 # Number of cycles rename is running system.cpu.rename.SQFullEvents 1551 # Number of times rename has blocked due to SQ full system.cpu.rename.SquashCycles 574 # Number of cycles rename is squashing system.cpu.rename.SquashedInsts 756 # Number of squashed instructions processed by rename system.cpu.rename.UnblockCycles 373748 # Number of cycles rename is unblocking system.cpu.rename.UndoneMaps 3339 # Number of HB maps that are undone due to squashing system.cpu.rename.int_rename_lookups 522273 # Number of integer rename lookups system.cpu.rename.serializeStallCycles 2665 # count of cycles rename stalled for serializing inst system.cpu.rename.serializingInsts 59 # count of serializing insts renamed system.cpu.rename.skidInsts 440564 # count of insts added to the skid buffer system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed system.cpu.rename.vec_rename_lookups 715730 # Number of vector rename lookups system.cpu.rob.rob_reads 3285427 # The number of ROB reads system.cpu.rob.rob_writes 1654917 # The number of ROB writes system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.vec_regfile_reads 715501 # number of vector regfile reads system.cpu.vec_regfile_writes 409039 # number of vector regfile writes system.cpu.workload.numSyscalls 7 # Number of system calls system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 619 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 1240635000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 479 # Transaction distribution system.membus.trans_dist::WritebackClean 48 # Transaction distribution system.membus.trans_dist::ReadExReq 84 # Transaction distribution system.membus.trans_dist::ReadExResp 84 # Transaction distribution system.membus.trans_dist::ReadCleanReq 325 # Transaction distribution system.membus.trans_dist::ReadSharedReq 155 # Transaction distribution system.membus.trans_dist::InvalidateReq 7 # Transaction distribution system.membus.pkt_count_system.cpu.icache.mem_side::system.mem_ctrls.port 697 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache.mem_side::system.mem_ctrls.port 485 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1182 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache.mem_side::system.mem_ctrls.port 23808 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache.mem_side::system.mem_ctrls.port 15296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 39104 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 571 # Request fanout histogram system.membus.snoop_fanout::mean 0.003503 # Request fanout histogram system.membus.snoop_fanout::stdev 0.059131 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 569 99.65% 99.65% # Request fanout histogram system.membus.snoop_fanout::1 2 0.35% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 571 # Request fanout histogram system.membus.reqLayer0.occupancy 961000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 1728000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 1270000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.cpu_voltage_domain.voltage 1 # Voltage in Volts system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 1240635000 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::.cpu.inst 20736 # Number of bytes read from this memory system.mem_ctrls.bytes_read::.cpu.data 15296 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 36032 # Number of bytes read from this memory system.mem_ctrls.bytes_inst_read::.cpu.inst 20736 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_inst_read::total 20736 # Number of instructions bytes read from this memory system.mem_ctrls.num_reads::.cpu.inst 324 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::.cpu.data 239 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::total 563 # Number of read requests responded to by this memory system.mem_ctrls.bw_read::.cpu.inst 16714021 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::.cpu.data 12329170 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::total 29043192 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::.cpu.inst 16714021 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::total 16714021 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_total::.cpu.inst 16714021 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::.cpu.data 12329170 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::total 29043192 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.avgPriority_.writebacks::samples 48.00 # Average QoS priority value for accepted requests system.mem_ctrls.avgPriority_.cpu.inst::samples 322.00 # Average QoS priority value for accepted requests system.mem_ctrls.avgPriority_.cpu.data::samples 239.00 # Average QoS priority value for accepted requests system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) system.mem_ctrls.priorityMaxLatency 0.002469778500 # per QoS priority maximum request to response latency (s) system.mem_ctrls.numReadWriteTurnArounds 1 # Number of turnarounds from READ to WRITE system.mem_ctrls.numWriteReadTurnArounds 1 # Number of turnarounds from WRITE to READ system.mem_ctrls.numStayReadState 1462 # Number of times bus staying in READ state system.mem_ctrls.numStayWriteState 17 # Number of times bus staying in WRITE state system.mem_ctrls.readReqs 564 # Number of read requests accepted system.mem_ctrls.writeReqs 48 # Number of write requests accepted system.mem_ctrls.readBursts 564 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 48 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrls.servicedByWrQ 3 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 50 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 2 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 27 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 34 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 39 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 48 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 26 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 93 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 67 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 97 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 25 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 2 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 7 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::13 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.avgRdQLen 1.01 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 24.71 # Average write queue length when enqueuing system.mem_ctrls.totQLat 6057000 # Total ticks spent queuing system.mem_ctrls.totBusLat 2805000 # Total ticks spent in databus transfers system.mem_ctrls.totMemAccLat 16575750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.avgQLat 10796.79 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 29546.79 # Average memory access latency per DRAM burst system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrls.readRowHits 438 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 11 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 78.07 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 22.92 # Row buffer hit rate for writes system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::6 564 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 48 # Write request sizes (log2) system.mem_ctrls.rdQLenPdf::0 351 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 142 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 51 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 15 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 3 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 118 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 295.593220 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::gmean 189.922189 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::stdev 297.129464 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::0-127 35 29.66% 29.66% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::128-255 32 27.12% 56.78% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::256-383 19 16.10% 72.88% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::384-511 12 10.17% 83.05% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 2 1.69% 84.75% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::640-767 4 3.39% 88.14% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::896-1023 3 2.54% 90.68% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 11 9.32% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 118 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 529 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 529 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::512-543 1 100.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::18 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads system.mem_ctrls.bytesReadDRAM 35904 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 192 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 1152 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 36096 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 3072 # Total written bytes from the system interface side system.mem_ctrls.avgRdBW 28.94 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 0.93 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 29.09 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 2.48 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 0.23 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 0.23 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.totGap 1240626500 # Total gap between requests system.mem_ctrls.avgGap 2027167.48 # Average gap between requests system.mem_ctrls.masterReadBytes::.cpu.inst 20608 # Per-master bytes read from memory system.mem_ctrls.masterReadBytes::.cpu.data 15296 # Per-master bytes read from memory system.mem_ctrls.masterWriteBytes::.writebacks 1152 # Per-master bytes write to memory system.mem_ctrls.masterReadRate::.cpu.inst 16610848.476788097993 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrls.masterReadRate::.cpu.data 12329170.142709178850 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrls.masterWriteRate::.writebacks 928556.747149645234 # Per-master bytes write to memory rate (Bytes/sec) system.mem_ctrls.masterReadAccesses::.cpu.inst 325 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.cpu.data 239 # Per-master read serviced memory accesses system.mem_ctrls.masterWriteAccesses::.writebacks 48 # Per-master write serviced memory accesses system.mem_ctrls.masterReadTotalLat::.cpu.inst 8839000 # Per-master read total memory access latency system.mem_ctrls.masterReadTotalLat::.cpu.data 7736750 # Per-master read total memory access latency system.mem_ctrls.masterWriteTotalLat::.writebacks 17186018250 # Per-master write total memory access latency system.mem_ctrls.masterReadAvgLat::.cpu.inst 27196.92 # Per-master read average memory access latency system.mem_ctrls.masterReadAvgLat::.cpu.data 32371.34 # Per-master read average memory access latency system.mem_ctrls.masterWriteAvgLat::.writebacks 358042046.88 # Per-master write average memory access latency system.mem_ctrls.pageHitRate 73.73 # Row buffer hit rate, read and write combined system.mem_ctrls.rank1.actEnergy 699720 # Energy for activate commands per rank (pJ) system.mem_ctrls.rank1.preEnergy 352935 # Energy for precharge commands per rank (pJ) system.mem_ctrls.rank1.readEnergy 2863140 # Energy for read commands per rank (pJ) system.mem_ctrls.rank1.writeEnergy 88740 # Energy for write commands per rank (pJ) system.mem_ctrls.rank1.refreshEnergy 97727760.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls.rank1.actBackEnergy 35351400 # Energy for active background per rank (pJ) system.mem_ctrls.rank1.preBackEnergy 446634240 # Energy for precharge background per rank (pJ) system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls.rank1.totalEnergy 583717935 # Total energy per rank (pJ) system.mem_ctrls.rank1.averagePower 470.499329 # Core power per rank (mW) system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls.rank1.memoryStateTime::IDLE 1160811250 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::REF 41340000 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::ACT 38483750 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls.rank0.actEnergy 221340 # Energy for activate commands per rank (pJ) system.mem_ctrls.rank0.preEnergy 94875 # Energy for precharge commands per rank (pJ) system.mem_ctrls.rank0.readEnergy 1135260 # Energy for read commands per rank (pJ) system.mem_ctrls.rank0.writeEnergy 5220 # Energy for write commands per rank (pJ) system.mem_ctrls.rank0.refreshEnergy 97727760.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls.rank0.actBackEnergy 29652540 # Energy for active background per rank (pJ) system.mem_ctrls.rank0.preBackEnergy 451433280 # Energy for precharge background per rank (pJ) system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls.rank0.totalEnergy 580270275 # Total energy per rank (pJ) system.mem_ctrls.rank0.averagePower 467.720381 # Core power per rank (mW) system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls.rank0.memoryStateTime::IDLE 1173351500 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::REF 41340000 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::ACT 25943500 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.pwrStateResidencyTicks::ON 1240635000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1240635000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 311656 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 311656 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 311656 # number of overall hits system.cpu.icache.overall_hits::total 311656 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 445 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 445 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 445 # number of overall misses system.cpu.icache.overall_misses::total 445 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 24204000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 24204000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 24204000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 24204000 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 312101 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 312101 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 312101 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 312101 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.001426 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001426 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.001426 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001426 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 54391.011236 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 54391.011236 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 54391.011236 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 54391.011236 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 76 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::.writebacks 48 # number of writebacks system.cpu.icache.writebacks::total 48 # number of writebacks system.cpu.icache.demand_mshr_hits::.cpu.inst 120 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 120 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::.cpu.inst 120 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 120 # number of overall MSHR hits system.cpu.icache.demand_mshr_misses::.cpu.inst 325 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 325 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 325 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 325 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 19046000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 19046000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 19046000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 19046000 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.001041 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001041 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.001041 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001041 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 58603.076923 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 58603.076923 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 58603.076923 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 58603.076923 # average overall mshr miss latency system.cpu.icache.replacements 48 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 311656 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 311656 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 445 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 445 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 24204000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 24204000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 312101 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 312101 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.001426 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001426 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 54391.011236 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 54391.011236 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 120 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 325 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 325 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 19046000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 19046000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.001041 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001041 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 58603.076923 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58603.076923 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1240635000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 233.535894 # Cycle average of tags in use system.cpu.icache.tags.total_refs 311980 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 324 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 962.901235 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 233.535894 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.456125 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.456125 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 212 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.539062 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 624526 # Number of tag accesses system.cpu.icache.tags.data_accesses 624526 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1240635000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1240635000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1240635000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1240635000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1240635000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 205756 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 205756 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 205760 # number of overall hits system.cpu.dcache.overall_hits::total 205760 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 888 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 888 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 890 # number of overall misses system.cpu.dcache.overall_misses::total 890 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 46181500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 46181500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 46181500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 46181500 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 206644 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 206644 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 206650 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 206650 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.004297 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.004297 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.004307 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004307 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 52006.193694 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 52006.193694 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 51889.325843 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 51889.325843 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 394 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.demand_mshr_hits::.cpu.data 645 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 645 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::.cpu.data 645 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 645 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses::.cpu.data 243 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 245 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 245 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 15182500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 15182500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 15324500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 15324500 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.001176 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001176 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.001186 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001186 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 62479.423868 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 62479.423868 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 62548.979592 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 62548.979592 # average overall mshr miss latency system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 102893 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 102893 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 473 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 473 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 20621500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 20621500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 103366 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 103366 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.004576 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004576 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 43597.251586 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 43597.251586 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 321 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 321 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 152 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 8990000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 8990000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.001471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 59144.736842 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59144.736842 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 102863 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 102863 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 408 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 25487000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 25487000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 103271 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 103271 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.003951 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003951 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 62468.137255 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 62468.137255 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 324 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 324 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 84 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 84 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 6126500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 6126500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.000813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 72934.523810 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72934.523810 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_hits::.cpu.data 4 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 4 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_accesses::.cpu.data 6 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 6 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.333333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.333333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 142000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 142000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 71000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 73000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 73000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 10428.571429 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 10428.571429 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 66000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 66000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 9428.571429 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 9428.571429 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 16 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 16 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 157500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 157500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 18 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.111111 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111111 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 78750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 54000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 54000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.055556 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.055556 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 54000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 54000 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_hits::.cpu.data 14 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 14 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 14 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 14 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1240635000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 222.825130 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 206036 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 246 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 837.544715 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 147000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 222.825130 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.217603 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.217603 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 246 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 225 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.240234 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 413610 # Number of tag accesses system.cpu.dcache.tags.data_accesses 413610 # Number of data accesses ---------- End Simulation Statistics ----------