---------- Begin Simulation Statistics ---------- final_tick 264650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 190751 # Simulator instruction rate (inst/s) host_mem_usage 818264 # Number of bytes of host memory used host_op_rate 191436 # Simulator op (including micro ops) rate (op/s) host_seconds 1.67 # Real time elapsed on the host host_tick_rate 158620315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 318234 # Number of instructions simulated sim_ops 319398 # Number of ops (including micro ops) simulated sim_seconds 0.000265 # Number of seconds simulated sim_ticks 264650000 # Number of ticks simulated system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 99.019899 # BTB Hit Percentage system.cpu.branchPred.BTBHits 33340 # Number of BTB hits system.cpu.branchPred.BTBLookups 33670 # Number of BTB lookups system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.branchPred.condIncorrect 753 # Number of conditional branches incorrect system.cpu.branchPred.condPredicted 51345 # Number of conditional branches predicted system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu.branchPred.indirectLookups 78 # Number of indirect predictor lookups. system.cpu.branchPred.indirectMisses 78 # Number of indirect misses. system.cpu.branchPred.lookups 52139 # Number of BP lookups system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPredindirectMispredicted 34 # Number of mispredicted indirect branches. system.cpu.cc_regfile_reads 150177 # number of cc regfile reads system.cpu.cc_regfile_writes 150150 # number of cc regfile writes system.cpu.commit.amos 0 # Number of atomic instructions committed system.cpu.commit.branchMispredicts 602 # The number of times a branch was mispredicted system.cpu.commit.branches 50618 # Number of branches committed system.cpu.commit.bw_lim_events 22149 # number cycles where commit BW limit reached system.cpu.commit.commitNonSpecStalls 23 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 2663 # The number of squashed insts skipped by commit system.cpu.commit.committedInsts 334636 # Number of instructions committed system.cpu.commit.committedOps 335800 # Number of ops (including micro ops) committed system.cpu.commit.committed_per_cycle::samples 507924 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.661123 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.886224 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 422422 83.17% 83.17% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 35542 7.00% 90.16% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 1584 0.31% 90.48% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 3104 0.61% 91.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 9307 1.83% 92.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 9735 1.92% 94.84% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 3884 0.76% 95.60% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 197 0.04% 95.64% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 22149 4.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 507924 # Number of insts commited each cycle system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.function_calls 117 # Number of function calls committed. system.cpu.commit.int_insts 220238 # Number of committed integer instructions. system.cpu.commit.loads 50017 # Number of loads committed system.cpu.commit.membars 14 # Number of memory barriers committed system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 137106 40.83% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 4 0.00% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 2 0.00% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatMisc 0 0.00% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 40.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 11 0.00% 40.84% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 40.84% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 32776 9.76% 50.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 32777 9.76% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 8 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdDiv 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 32768 9.76% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAes 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 70.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdPredAlu 16385 4.88% 75.00% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 50017 14.89% 89.89% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 33944 10.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 335800 # Class of committed instruction system.cpu.commit.refs 83961 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.vec_insts 114769 # Number of committed Vector instructions. system.cpu.committedInsts 318234 # Number of Instructions Simulated system.cpu.committedOps 319398 # Number of Ops (including micro ops) Simulated system.cpu.cpi 1.663245 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.663245 # CPI: Total CPI of All Threads system.cpu.decode.BlockedCycles 270248 # Number of cycles decode is blocked system.cpu.decode.BranchMispred 157 # Number of times decode detected a branch misprediction system.cpu.decode.BranchResolved 33308 # Number of times decode resolved a branch system.cpu.decode.DecodedInsts 341094 # Number of instructions handled by decode system.cpu.decode.IdleCycles 84972 # Number of cycles decode is idle system.cpu.decode.RunCycles 145094 # Number of cycles decode is running system.cpu.decode.SquashCycles 613 # Number of cycles decode is squashing system.cpu.decode.SquashedInsts 1527 # Number of squashed instructions handled by decode system.cpu.decode.UnblockCycles 7719 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 52139 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 103268 # Number of cache lines fetched system.cpu.fetch.Cycles 396067 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 339 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 342634 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 1528 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.098505 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 111815 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 33626 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.647333 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 508646 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.677878 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.081088 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 337026 66.26% 66.26% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 66966 13.17% 79.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 36128 7.10% 86.53% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 68526 13.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 508646 # Number of instructions fetched each cycle (Total) system.cpu.idleCycles 20655 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.branchMispredicts 622 # Number of branch mispredicts detected at execute system.cpu.iew.exec_branches 50860 # Number of branches executed system.cpu.iew.exec_nop 16546 # number of nop insts executed system.cpu.iew.exec_rate 0.676071 # Inst execution rate system.cpu.iew.exec_refs 120907 # number of memory reference insts executed system.cpu.iew.exec_stores 34043 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 109 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 50667 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 34208 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 339067 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 86864 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 582 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 357845 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 703 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 613 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 702 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 5280 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.squashedLoads 650 # Number of loads squashed system.cpu.iew.lsq.thread0.squashedStores 264 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 490 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly system.cpu.iew.wb_consumers 357859 # num instructions consuming a value system.cpu.iew.wb_count 321067 # cumulative count of insts written-back system.cpu.iew.wb_fanout 0.497120 # average fanout of values written-back system.cpu.iew.wb_producers 177899 # num instructions producing a value system.cpu.iew.wb_rate 0.606587 # insts written-back per cycle system.cpu.iew.wb_sent 321144 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 399275 # number of integer regfile reads system.cpu.int_regfile_writes 105326 # number of integer regfile writes system.cpu.ipc 0.601234 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.601234 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 122360 34.14% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 4 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 2 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 11 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 32780 9.15% 43.29% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 32777 9.14% 52.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 8 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 52.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 32768 9.14% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdAes 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 61.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdPredAlu 16513 4.61% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 87119 24.31% 90.49% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 34083 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 358427 # Type of FU issued system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fu_busy_cnt 41627 # FU busy when requested system.cpu.iq.fu_busy_rate 0.116138 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 1140 2.74% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMisc 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 2417 5.81% 8.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 20 0.05% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdDiv 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.59% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 1 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAes 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAesMix 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 33396 80.23% 88.82% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 4653 11.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 211493 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 927306 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 206298 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_writes 210571 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 322493 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 358427 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 3122 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 2073 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.issued_per_cycle::samples 508646 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.704669 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.004233 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 287848 56.59% 56.59% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 133215 26.19% 82.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 49545 9.74% 92.52% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 29897 5.88% 98.40% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 4277 0.84% 99.24% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 3861 0.76% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 508646 # Number of insts issued each cycle system.cpu.iq.rate 0.677170 # Inst issue rate system.cpu.iq.vec_alu_accesses 188559 # Number of vector alu accesses system.cpu.iq.vec_inst_queue_reads 339920 # Number of vector instruction queue reads system.cpu.iq.vec_inst_queue_wakeup_accesses 114769 # Number of vector instruction queue wakeup accesses system.cpu.iq.vec_inst_queue_writes 115075 # Number of vector instruction queue writes system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 50667 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 34208 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 1023051 # number of misc regfile reads system.cpu.misc_regfile_writes 32825 # number of misc regfile writes system.cpu.numCycles 529301 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.pred_regfile_reads 188107 # number of predicate regfile reads system.cpu.pred_regfile_writes 49282 # number of predicate regfile writes system.cpu.rename.BlockCycles 258242 # Number of cycles rename is blocking system.cpu.rename.CommittedMaps 417770 # Number of HB maps that are committed system.cpu.rename.IdleCycles 89851 # Number of cycles rename is idle system.cpu.rename.LQFullEvents 8 # Number of times rename has blocked due to LQ full system.cpu.rename.ROBFullEvents 7519 # Number of times rename has blocked due to ROB full system.cpu.rename.RenameLookups 1148424 # Number of register rename lookups that rename has made system.cpu.rename.RenamedInsts 339586 # Number of instructions processed by rename system.cpu.rename.RenamedOperands 421441 # Number of destination operands rename has renamed system.cpu.rename.RunCycles 147020 # Number of cycles rename is running system.cpu.rename.SQFullEvents 953 # Number of times rename has blocked due to SQ full system.cpu.rename.SquashCycles 613 # Number of cycles rename is squashing system.cpu.rename.SquashedInsts 601 # Number of squashed instructions processed by rename system.cpu.rename.UnblockCycles 10565 # Number of cycles rename is unblocking system.cpu.rename.UndoneMaps 3671 # Number of HB maps that are undone due to squashing system.cpu.rename.int_rename_lookups 340707 # Number of integer rename lookups system.cpu.rename.serializeStallCycles 2355 # count of cycles rename stalled for serializing inst system.cpu.rename.serializingInsts 59 # count of serializing insts renamed system.cpu.rename.skidInsts 16078 # count of insts added to the skid buffer system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed system.cpu.rename.vec_pred_rename_lookups 131596 # Number of vector predicate rename lookups system.cpu.rename.vec_rename_lookups 98450 # Number of vector rename lookups system.cpu.rob.rob_reads 824134 # The number of ROB reads system.cpu.rob.rob_writes 677650 # The number of ROB writes system.cpu.timesIdled 253 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.vec_regfile_reads 98405 # number of vector regfile reads system.cpu.vec_regfile_writes 81958 # number of vector regfile writes system.cpu.workload.numSyscalls 8 # Number of system calls system.membus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 6879 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 15046 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 264650000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 6839 # Transaction distribution system.membus.trans_dist::WritebackDirty 1335 # Transaction distribution system.membus.trans_dist::WritebackClean 43 # Transaction distribution system.membus.trans_dist::CleanEvict 5500 # Transaction distribution system.membus.trans_dist::ReadExReq 90 # Transaction distribution system.membus.trans_dist::ReadExResp 90 # Transaction distribution system.membus.trans_dist::ReadCleanReq 309 # Transaction distribution system.membus.trans_dist::ReadSharedReq 6531 # Transaction distribution system.membus.trans_dist::InvalidateReq 1238 # Transaction distribution system.membus.pkt_count_system.cpu.icache.mem_side::system.mem_ctrls.port 660 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache.mem_side::system.mem_ctrls.port 21315 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 21975 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache.mem_side::system.mem_ctrls.port 22464 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache.mem_side::system.mem_ctrls.port 509184 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 531648 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 8168 # Request fanout histogram system.membus.snoop_fanout::mean 0.000245 # Request fanout histogram system.membus.snoop_fanout::stdev 0.015647 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 8166 99.98% 99.98% # Request fanout histogram system.membus.snoop_fanout::1 2 0.02% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 8168 # Request fanout histogram system.membus.reqLayer0.occupancy 22210500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 8.4 # Layer utilization (%) system.membus.respLayer1.occupancy 1638750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) system.membus.respLayer2.occupancy 34440250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 13.0 # Layer utilization (%) system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.cpu_voltage_domain.voltage 1 # Voltage in Volts system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 264650000 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::.cpu.inst 19712 # Number of bytes read from this memory system.mem_ctrls.bytes_read::.cpu.data 423744 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 443456 # Number of bytes read from this memory system.mem_ctrls.bytes_inst_read::.cpu.inst 19712 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_inst_read::total 19712 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_written::.writebacks 85440 # Number of bytes written to this memory system.mem_ctrls.bytes_written::total 85440 # Number of bytes written to this memory system.mem_ctrls.num_reads::.cpu.inst 308 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::.cpu.data 6621 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::total 6929 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::.writebacks 1335 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1335 # Number of write requests responded to by this memory system.mem_ctrls.bw_read::.cpu.inst 74483280 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::.cpu.data 1601148687 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::total 1675631967 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::.cpu.inst 74483280 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::total 74483280 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_write::.writebacks 322841489 # Write bandwidth from this memory (bytes/s) system.mem_ctrls.bw_write::total 322841489 # Write bandwidth from this memory (bytes/s) system.mem_ctrls.bw_total::.writebacks 322841489 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::.cpu.inst 74483280 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::.cpu.data 1601148687 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::total 1998473456 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.avgPriority_.writebacks::samples 1177.00 # Average QoS priority value for accepted requests system.mem_ctrls.avgPriority_.cpu.inst::samples 307.00 # Average QoS priority value for accepted requests system.mem_ctrls.avgPriority_.cpu.data::samples 6620.00 # Average QoS priority value for accepted requests system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) system.mem_ctrls.priorityMaxLatency 0.000041304750 # per QoS priority maximum request to response latency (s) system.mem_ctrls.numReadWriteTurnArounds 72 # Number of turnarounds from READ to WRITE system.mem_ctrls.numWriteReadTurnArounds 72 # Number of turnarounds from WRITE to READ system.mem_ctrls.numStayReadState 14847 # Number of times bus staying in READ state system.mem_ctrls.numStayWriteState 1091 # Number of times bus staying in WRITE state system.mem_ctrls.readReqs 6930 # Number of read requests accepted system.mem_ctrls.writeReqs 1378 # Number of write requests accepted system.mem_ctrls.readBursts 6930 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1378 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrls.servicedByWrQ 3 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 201 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 182 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 136 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 173 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 142 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 136 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 381 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 673 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 658 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 694 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 771 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 738 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 693 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 711 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 551 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 153 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 135 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 131 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 128 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 128 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 130 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 129 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 73 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 2 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 2 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 47 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 24 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 27 # Per bank write bursts system.mem_ctrls.perBankWrBursts::13 72 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 129 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 128 # Per bank write bursts system.mem_ctrls.avgRdQLen 1.90 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 25.00 # Average write queue length when enqueuing system.mem_ctrls.totQLat 74373000 # Total ticks spent queuing system.mem_ctrls.totBusLat 34635000 # Total ticks spent in databus transfers system.mem_ctrls.totMemAccLat 204254250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.avgQLat 10736.68 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 29486.68 # Average memory access latency per DRAM burst system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrls.readRowHits 6264 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 1051 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 90.43 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 89.29 # Row buffer hit rate for writes system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::6 6930 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1378 # Write request sizes (log2) system.mem_ctrls.rdQLenPdf::0 2791 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 1533 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 1512 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 1087 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 4 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 59 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 70 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 75 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 75 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 74 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 78 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 79 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 75 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 76 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 74 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 78 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 80 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 72 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 81 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 73 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 753 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 683.771580 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::gmean 495.744694 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::stdev 394.762480 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::0-127 62 8.23% 8.23% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::128-255 118 15.67% 23.90% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::256-383 59 7.84% 31.74% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::384-511 34 4.52% 36.25% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 28 3.72% 39.97% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::640-767 30 3.98% 43.96% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 15 1.99% 45.95% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::896-1023 13 1.73% 47.68% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 394 52.32% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 753 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 72 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 95.875000 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 82.790103 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::stdev 115.734876 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::0-63 4 5.56% 5.56% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::64-127 66 91.67% 97.22% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::128-191 1 1.39% 98.61% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::1024-1087 1 1.39% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 72 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 72 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 72 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 72 # Writes before turning the bus around for reads system.mem_ctrls.bytesReadDRAM 443328 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 192 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 73728 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 443520 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 88192 # Total written bytes from the system interface side system.mem_ctrls.avgRdBW 1675.15 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 278.59 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 1675.87 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 333.24 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 15.26 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 13.09 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 2.18 # Data bus utilization in percentage for writes system.mem_ctrls.totGap 264636500 # Total gap between requests system.mem_ctrls.avgGap 31853.21 # Average gap between requests system.mem_ctrls.masterReadBytes::.cpu.inst 19648 # Per-master bytes read from memory system.mem_ctrls.masterReadBytes::.cpu.data 423680 # Per-master bytes read from memory system.mem_ctrls.masterWriteBytes::.writebacks 73728 # Per-master bytes write to memory system.mem_ctrls.masterReadRate::.cpu.inst 74241450.972983181477 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrls.masterReadRate::.cpu.data 1600906858.114490747452 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrls.masterWriteRate::.writebacks 278586812.771585106850 # Per-master bytes write to memory rate (Bytes/sec) system.mem_ctrls.masterReadAccesses::.cpu.inst 309 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.cpu.data 6621 # Per-master read serviced memory accesses system.mem_ctrls.masterWriteAccesses::.writebacks 1378 # Per-master write serviced memory accesses system.mem_ctrls.masterReadTotalLat::.cpu.inst 8417250 # Per-master read total memory access latency system.mem_ctrls.masterReadTotalLat::.cpu.data 195837000 # Per-master read total memory access latency system.mem_ctrls.masterWriteTotalLat::.writebacks 6148176000 # Per-master write total memory access latency system.mem_ctrls.masterReadAvgLat::.cpu.inst 27240.29 # Per-master read average memory access latency system.mem_ctrls.masterReadAvgLat::.cpu.data 29578.16 # Per-master read average memory access latency system.mem_ctrls.masterWriteAvgLat::.writebacks 4461666.18 # Per-master write average memory access latency system.mem_ctrls.pageHitRate 90.26 # Row buffer hit rate, read and write combined system.mem_ctrls.rank1.actEnergy 3327240 # Energy for activate commands per rank (pJ) system.mem_ctrls.rank1.preEnergy 1749495 # Energy for precharge commands per rank (pJ) system.mem_ctrls.rank1.readEnergy 31744440 # Energy for read commands per rank (pJ) system.mem_ctrls.rank1.writeEnergy 2244600 # Energy for write commands per rank (pJ) system.mem_ctrls.rank1.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls.rank1.actBackEnergy 117129870 # Energy for active background per rank (pJ) system.mem_ctrls.rank1.preBackEnergy 2989920 # Energy for precharge background per rank (pJ) system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls.rank1.totalEnergy 179468685 # Total energy per rank (pJ) system.mem_ctrls.rank1.averagePower 678.135972 # Core power per rank (mW) system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls.rank1.memoryStateTime::IDLE 6663750 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::REF 8580000 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::ACT 249406250 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls.rank0.actEnergy 2127720 # Energy for activate commands per rank (pJ) system.mem_ctrls.rank0.preEnergy 1108140 # Energy for precharge commands per rank (pJ) system.mem_ctrls.rank0.readEnergy 17714340 # Energy for read commands per rank (pJ) system.mem_ctrls.rank0.writeEnergy 3768840 # Energy for write commands per rank (pJ) system.mem_ctrls.rank0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls.rank0.actBackEnergy 111735960 # Energy for active background per rank (pJ) system.mem_ctrls.rank0.preBackEnergy 7532160 # Energy for precharge background per rank (pJ) system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls.rank0.totalEnergy 164270280 # Total energy per rank (pJ) system.mem_ctrls.rank0.averagePower 620.707652 # Core power per rank (mW) system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls.rank0.memoryStateTime::IDLE 18350250 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::REF 8580000 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::ACT 237719750 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.pwrStateResidencyTicks::ON 264650000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 264650000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 102861 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 102861 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 102861 # number of overall hits system.cpu.icache.overall_hits::total 102861 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 407 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 407 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 407 # number of overall misses system.cpu.icache.overall_misses::total 407 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 22442000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 22442000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 22442000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 22442000 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 103268 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 103268 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 103268 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 103268 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.003941 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.003941 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.003941 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.003941 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 55140.049140 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 55140.049140 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 55140.049140 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 55140.049140 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::.writebacks 43 # number of writebacks system.cpu.icache.writebacks::total 43 # number of writebacks system.cpu.icache.demand_mshr_hits::.cpu.inst 98 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 98 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::.cpu.inst 98 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 98 # number of overall MSHR hits system.cpu.icache.demand_mshr_misses::.cpu.inst 309 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 309 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 309 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 309 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 18150000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 18150000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 18150000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 18150000 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.002992 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.002992 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.002992 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.002992 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 58737.864078 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 58737.864078 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 58737.864078 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 58737.864078 # average overall mshr miss latency system.cpu.icache.replacements 43 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 102861 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 102861 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 407 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 407 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 22442000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 22442000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 103268 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 103268 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.003941 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003941 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 55140.049140 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 55140.049140 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 98 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 309 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 309 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 18150000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 18150000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.002992 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002992 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 58737.864078 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58737.864078 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 264650000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 236.308018 # Cycle average of tags in use system.cpu.icache.tags.total_refs 103169 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 334.964286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 236.308018 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.461539 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.461539 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 265 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.517578 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 206844 # Number of tag accesses system.cpu.icache.tags.data_accesses 206844 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 264650000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 264650000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 264650000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 264650000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 264650000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 301168 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 301168 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 301172 # number of overall hits system.cpu.dcache.overall_hits::total 301172 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 12409 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 12409 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 12411 # number of overall misses system.cpu.dcache.overall_misses::total 12411 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 603747861 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 603747861 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 603747861 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 603747861 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 313577 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 313577 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 313583 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 313583 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.039572 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.039572 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.039578 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.039578 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 48654.030220 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 48654.030220 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 48646.189751 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 48646.189751 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 152753 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5291 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.870346 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::.writebacks 1335 # number of writebacks system.cpu.dcache.writebacks::total 1335 # number of writebacks system.cpu.dcache.demand_mshr_hits::.cpu.data 4554 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 4554 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::.cpu.data 4554 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 4554 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses::.cpu.data 7855 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 7855 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 7857 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 7857 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 423066388 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 423066388 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 423208388 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 423208388 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.025050 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025050 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.025056 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025056 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 53859.501973 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 53859.501973 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 53863.865088 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53863.865088 # average overall mshr miss latency system.cpu.dcache.replacements 6835 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 171347 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 171347 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 9996 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 9996 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 561922000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 561922000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 181343 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 181343 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.055122 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.055122 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 56214.685874 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 56214.685874 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 3469 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 3469 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 6527 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 6527 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 404395027 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 404395027 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.035993 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035993 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 61957.258618 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61957.258618 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 739 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 739 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 416 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 416 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 25679000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 25679000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 1155 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1155 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.360173 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.360173 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 61728.365385 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 61728.365385 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 90 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 90 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 6141500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 6141500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.077922 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.077922 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 68238.888889 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68238.888889 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_hits::.cpu.data 4 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 4 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_accesses::.cpu.data 6 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 6 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.333333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.333333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 142000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 142000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 71000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_hits::.cpu.data 129082 # number of WriteLineReq hits system.cpu.dcache.WriteLineReq_hits::total 129082 # number of WriteLineReq hits system.cpu.dcache.WriteLineReq_misses::.cpu.data 1997 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 1997 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 16146861 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 16146861 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_accesses::.cpu.data 131079 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 131079 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.015235 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 0.015235 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 8085.558838 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 8085.558838 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_mshr_hits::.cpu.data 759 # number of WriteLineReq MSHR hits system.cpu.dcache.WriteLineReq_mshr_hits::total 759 # number of WriteLineReq MSHR hits system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 1238 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 1238 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 12529861 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 12529861 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.009445 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.009445 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 10121.050889 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 10121.050889 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_misses::.cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 180500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 180500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 16 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.187500 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.187500 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 60166.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 60166.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 121000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 121000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.125000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.125000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 60500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 60500 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_hits::.cpu.data 14 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 14 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 14 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 14 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264650000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 938.124032 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 309058 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 7859 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 39.325359 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 152000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 938.124032 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.916137 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.916137 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 761 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 635085 # Number of tag accesses system.cpu.dcache.tags.data_accesses 635085 # Number of data accesses ---------- End Simulation Statistics ----------