---------- Begin Simulation Statistics ---------- final_tick 463987630000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 1615891 # Simulator instruction rate (inst/s) host_mem_usage 803196 # Number of bytes of host memory used host_op_rate 1616215 # Simulator op (including micro ops) rate (op/s) host_seconds 130.23 # Real time elapsed on the host host_tick_rate 3562918711 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 210432114 # Number of instructions simulated sim_ops 210474590 # Number of ops (including micro ops) simulated sim_seconds 0.463988 # Number of seconds simulated sim_ticks 463987630000 # Number of ticks simulated system.cpu.Branches 41933575 # Number of branches fetched system.cpu.committedInsts 210432114 # Number of instructions committed system.cpu.committedOps 210474590 # Number of ops (including micro ops) committed system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 463987630 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 463987630 # Number of busy cycles system.cpu.num_cc_register_reads 188491389 # number of times the CC registers were read system.cpu.num_cc_register_writes 188523350 # number of times the CC registers were written system.cpu.num_conditional_control_insts 41930082 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_func_calls 2969 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_int_alu_accesses 168318416 # Number of integer alu accesses system.cpu.num_int_insts 168318416 # number of integer instructions system.cpu.num_int_register_reads 316343770 # number of times the integer registers were read system.cpu.num_int_register_writes 168288919 # number of times the integer registers were written system.cpu.num_load_insts 21013256 # Number of load instructions system.cpu.num_mem_refs 21137615 # number of memory refs system.cpu.num_store_insts 124359 # Number of store instructions system.cpu.num_vec_alu_accesses 393353 # Number of vector alu accesses system.cpu.num_vec_insts 393353 # number of vector instructions system.cpu.num_vec_register_reads 426121 # number of times the vector registers were read system.cpu.num_vec_register_writes 327710 # number of times the vector registers were written system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 188910957 89.75% 89.75% # Class of executed instruction system.cpu.op_class::IntMult 131100 0.06% 89.82% # Class of executed instruction system.cpu.op_class::IntDiv 3 0.00% 89.82% # Class of executed instruction system.cpu.op_class::FloatAdd 32768 0.02% 89.83% # Class of executed instruction system.cpu.op_class::FloatCmp 32768 0.02% 89.85% # Class of executed instruction system.cpu.op_class::FloatCvt 65536 0.03% 89.88% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 89.88% # Class of executed instruction system.cpu.op_class::FloatMultAcc 65536 0.03% 89.91% # Class of executed instruction system.cpu.op_class::FloatDiv 32768 0.02% 89.93% # Class of executed instruction system.cpu.op_class::FloatMisc 32772 0.02% 89.94% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 89.94% # Class of executed instruction system.cpu.op_class::SimdAdd 5 0.00% 89.94% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 89.94% # Class of executed instruction system.cpu.op_class::SimdAlu 4 0.00% 89.94% # Class of executed instruction system.cpu.op_class::SimdCmp 4 0.00% 89.94% # Class of executed instruction system.cpu.op_class::SimdCvt 0 0.00% 89.94% # Class of executed instruction system.cpu.op_class::SimdMisc 32775 0.02% 89.96% # Class of executed instruction system.cpu.op_class::SimdMult 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdMultAcc 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdShift 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdShiftAcc 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdDiv 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdSqrt 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatAdd 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatAlu 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdReduceAdd 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdReduceAlu 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdReduceCmp 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatReduceAdd 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdFloatReduceCmp 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdAes 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdAesMix 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdSha1Hash 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdSha1Hash2 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdSha256Hash 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdSha256Hash2 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdShaSigma2 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdShaSigma3 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::SimdPredAlu 0 0.00% 89.96% # Class of executed instruction system.cpu.op_class::MemRead 21013256 9.98% 99.94% # Class of executed instruction system.cpu.op_class::MemWrite 124359 0.06% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 210474612 # Class of executed instruction system.cpu.workload.numSyscalls 21 # Number of system calls system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_single_requests 10557 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_single_snoops 232 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.tot_requests 22394 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.tot_snoops 232 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 3202 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 10702 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1085 # Transaction distribution system.membus.trans_dist::WritebackDirty 2480 # Transaction distribution system.membus.trans_dist::CleanEvict 722 # Transaction distribution system.membus.trans_dist::ReadExReq 6407 # Transaction distribution system.membus.trans_dist::ReadExResp 6407 # Transaction distribution system.membus.trans_dist::ReadSharedReq 1085 # Transaction distribution system.membus.trans_dist::InvalidateReq 8 # Transaction distribution system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 18194 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 18194 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 638208 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 638208 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7500 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 7500 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7500 # Request fanout histogram system.membus.reqLayer0.occupancy 20622000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 39561500 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) system.l2bus.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 1305 # Transaction distribution system.l2bus.trans_dist::WritebackDirty 12081 # Transaction distribution system.l2bus.trans_dist::CleanEvict 1880 # Transaction distribution system.l2bus.trans_dist::ReadExReq 10524 # Transaction distribution system.l2bus.trans_dist::ReadExResp 10524 # Transaction distribution system.l2bus.trans_dist::ReadSharedReq 1305 # Transaction distribution system.l2bus.trans_dist::InvalidateReq 8 # Transaction distribution system.l2bus.trans_dist::InvalidateResp 8 # Transaction distribution system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 2723 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 31508 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count::total 34231 # Packet count per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 63552 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 1307968 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 1371520 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 3404 # Total snoops (count) system.l2bus.snoopTraffic 158720 # Total snoop traffic (bytes) system.l2bus.snoop_fanout::samples 15241 # Request fanout histogram system.l2bus.snoop_fanout::mean 0.015288 # Request fanout histogram system.l2bus.snoop_fanout::stdev 0.122699 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.l2bus.snoop_fanout::0 15008 98.47% 98.47% # Request fanout histogram system.l2bus.snoop_fanout::1 233 1.53% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 15241 # Request fanout histogram system.l2bus.respLayer1.occupancy 32516000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.0 # Layer utilization (%) system.l2bus.reqLayer0.occupancy 41596000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.l2bus.respLayer0.occupancy 2979000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 0.0 # Layer utilization (%) system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.cpu.numPwrStateTransitions 1 # Number of power state transitions system.cpu.pwrStateResidencyTicks::ON 463987630000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 210431144 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 210431144 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 210431144 # number of overall hits system.cpu.icache.overall_hits::total 210431144 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 993 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 993 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 993 # number of overall misses system.cpu.icache.overall_misses::total 993 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 91671000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 91671000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 91671000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 91671000 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 210432137 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 210432137 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 210432137 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 210432137 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 92317.220544 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 92317.220544 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 92317.220544 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 92317.220544 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.demand_mshr_misses::.cpu.inst 993 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 993 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 993 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 993 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 89685000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 89685000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 89685000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 89685000 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 90317.220544 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 90317.220544 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 90317.220544 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 90317.220544 # average overall mshr miss latency system.cpu.icache.replacements 737 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 210431144 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 210431144 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 993 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 993 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 91671000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 91671000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 210432137 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 210432137 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 92317.220544 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 92317.220544 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 993 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 993 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 89685000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 89685000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 90317.220544 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90317.220544 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 255.971064 # Cycle average of tags in use system.cpu.icache.tags.total_refs 210432137 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 993 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 211915.545821 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 107000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 255.971064 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.999887 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999887 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 256 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 420865267 # Number of tag accesses system.cpu.icache.tags.data_accesses 420865267 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 21126713 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 21126713 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 21126719 # number of overall hits system.cpu.dcache.overall_hits::total 21126719 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 10841 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 10841 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 10848 # number of overall misses system.cpu.dcache.overall_misses::total 10848 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 780158000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 780158000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 780158000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 780158000 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 21137554 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 21137554 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 21137567 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21137567 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.000513 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000513 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.000513 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000513 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 71963.656489 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 71963.656489 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 71917.219764 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 71917.219764 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::.writebacks 9601 # number of writebacks system.cpu.dcache.writebacks::total 9601 # number of writebacks system.cpu.dcache.demand_mshr_hits::.cpu.data 4 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::.cpu.data 4 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses::.cpu.data 10837 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 10837 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 10844 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 10844 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 757857000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 757857000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 758873000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 758873000 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.000513 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000513 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.000513 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000513 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 69932.361355 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 69932.361355 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 69980.911103 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 69980.911103 # average overall mshr miss latency system.cpu.dcache.replacements 9820 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 21012945 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21012945 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 309 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 26953000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 26953000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 21013254 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 21013254 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.000015 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000015 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 87226.537217 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 87226.537217 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 4 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 305 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 305 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 25716000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 25716000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000015 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 84314.754098 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84314.754098 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 113768 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 113768 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 10524 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 10524 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 752773000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 752773000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 124292 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 124292 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.084672 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.084672 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 71529.171418 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 71529.171418 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 10524 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 10524 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 731725000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 731725000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.084672 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084672 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 69529.171418 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69529.171418 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_hits::.cpu.data 6 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 6 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_misses::.cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_accesses::.cpu.data 13 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 13 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.538462 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.538462 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 7 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 7 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 1016000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1016000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.538462 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.538462 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 145142.857143 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 145142.857143 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_misses::.cpu.data 8 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 8 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 432000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 432000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_accesses::.cpu.data 8 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 8 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 54000 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 54000 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 8 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 8 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 416000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 416000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 52000 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 52000 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 64 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 64 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 64 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits::.cpu.data 64 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 64 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 64 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 64 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 1023.478200 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 21137691 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 10844 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 1949.252213 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 236000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 1023.478200 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.999490 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999490 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1024 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 42286234 # Number of tag accesses system.cpu.dcache.tags.data_accesses 42286234 # Number of data accesses system.l2cache.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.l2cache.demand_hits::.cpu.inst 146 # number of demand (read+write) hits system.l2cache.demand_hits::.cpu.data 4191 # number of demand (read+write) hits system.l2cache.demand_hits::total 4337 # number of demand (read+write) hits system.l2cache.overall_hits::.cpu.inst 146 # number of overall hits system.l2cache.overall_hits::.cpu.data 4191 # number of overall hits system.l2cache.overall_hits::total 4337 # number of overall hits system.l2cache.demand_misses::.cpu.inst 847 # number of demand (read+write) misses system.l2cache.demand_misses::.cpu.data 6645 # number of demand (read+write) misses system.l2cache.demand_misses::total 7492 # number of demand (read+write) misses system.l2cache.overall_misses::.cpu.inst 847 # number of overall misses system.l2cache.overall_misses::.cpu.data 6645 # number of overall misses system.l2cache.overall_misses::total 7492 # number of overall misses system.l2cache.demand_miss_latency::.cpu.inst 83631000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::.cpu.data 637936000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::total 721567000 # number of demand (read+write) miss cycles system.l2cache.overall_miss_latency::.cpu.inst 83631000 # number of overall miss cycles system.l2cache.overall_miss_latency::.cpu.data 637936000 # number of overall miss cycles system.l2cache.overall_miss_latency::total 721567000 # number of overall miss cycles system.l2cache.demand_accesses::.cpu.inst 993 # number of demand (read+write) accesses system.l2cache.demand_accesses::.cpu.data 10836 # number of demand (read+write) accesses system.l2cache.demand_accesses::total 11829 # number of demand (read+write) accesses system.l2cache.overall_accesses::.cpu.inst 993 # number of overall (read+write) accesses system.l2cache.overall_accesses::.cpu.data 10836 # number of overall (read+write) accesses system.l2cache.overall_accesses::total 11829 # number of overall (read+write) accesses system.l2cache.demand_miss_rate::.cpu.inst 0.852971 # miss rate for demand accesses system.l2cache.demand_miss_rate::.cpu.data 0.613234 # miss rate for demand accesses system.l2cache.demand_miss_rate::total 0.633359 # miss rate for demand accesses system.l2cache.overall_miss_rate::.cpu.inst 0.852971 # miss rate for overall accesses system.l2cache.overall_miss_rate::.cpu.data 0.613234 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.633359 # miss rate for overall accesses system.l2cache.demand_avg_miss_latency::.cpu.inst 98737.898465 # average overall miss latency system.l2cache.demand_avg_miss_latency::.cpu.data 96002.407825 # average overall miss latency system.l2cache.demand_avg_miss_latency::total 96311.665777 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.inst 98737.898465 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.data 96002.407825 # average overall miss latency system.l2cache.overall_avg_miss_latency::total 96311.665777 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2cache.writebacks::.writebacks 2480 # number of writebacks system.l2cache.writebacks::total 2480 # number of writebacks system.l2cache.demand_mshr_misses::.cpu.inst 847 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::.cpu.data 6645 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::total 7492 # number of demand (read+write) MSHR misses system.l2cache.overall_mshr_misses::.cpu.inst 847 # number of overall MSHR misses system.l2cache.overall_mshr_misses::.cpu.data 6645 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 7492 # number of overall MSHR misses system.l2cache.demand_mshr_miss_latency::.cpu.inst 66691000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::.cpu.data 505036000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::total 571727000 # number of demand (read+write) MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.inst 66691000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.data 505036000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::total 571727000 # number of overall MSHR miss cycles system.l2cache.demand_mshr_miss_rate::.cpu.inst 0.852971 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::.cpu.data 0.613234 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::total 0.633359 # mshr miss rate for demand accesses system.l2cache.overall_mshr_miss_rate::.cpu.inst 0.852971 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::.cpu.data 0.613234 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.633359 # mshr miss rate for overall accesses system.l2cache.demand_avg_mshr_miss_latency::.cpu.inst 78737.898465 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::.cpu.data 76002.407825 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::total 76311.665777 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.inst 78737.898465 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.data 76002.407825 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 76311.665777 # average overall mshr miss latency system.l2cache.replacements 3404 # number of replacements system.l2cache.WritebackDirty_hits::.writebacks 9601 # number of WritebackDirty hits system.l2cache.WritebackDirty_hits::total 9601 # number of WritebackDirty hits system.l2cache.WritebackDirty_accesses::.writebacks 9601 # number of WritebackDirty accesses(hits+misses) system.l2cache.WritebackDirty_accesses::total 9601 # number of WritebackDirty accesses(hits+misses) system.l2cache.CleanEvict_mshr_misses::.writebacks 30 # number of CleanEvict MSHR misses system.l2cache.CleanEvict_mshr_misses::total 30 # number of CleanEvict MSHR misses system.l2cache.CleanEvict_mshr_miss_rate::.writebacks inf # mshr miss rate for CleanEvict accesses system.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2cache.ReadExReq_hits::.cpu.data 4117 # number of ReadExReq hits system.l2cache.ReadExReq_hits::total 4117 # number of ReadExReq hits system.l2cache.ReadExReq_misses::.cpu.data 6407 # number of ReadExReq misses system.l2cache.ReadExReq_misses::total 6407 # number of ReadExReq misses system.l2cache.ReadExReq_miss_latency::.cpu.data 613695000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_miss_latency::total 613695000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_accesses::.cpu.data 10524 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 10524 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_miss_rate::.cpu.data 0.608799 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_miss_rate::total 0.608799 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_miss_latency::.cpu.data 95785.078820 # average ReadExReq miss latency system.l2cache.ReadExReq_avg_miss_latency::total 95785.078820 # average ReadExReq miss latency system.l2cache.ReadExReq_mshr_misses::.cpu.data 6407 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 6407 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_miss_latency::.cpu.data 485555000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_latency::total 485555000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::.cpu.data 0.608799 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 0.608799 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_mshr_miss_latency::.cpu.data 75785.078820 # average ReadExReq mshr miss latency system.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.078820 # average ReadExReq mshr miss latency system.l2cache.ReadSharedReq_hits::.cpu.inst 146 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::.cpu.data 74 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 220 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_misses::.cpu.inst 847 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::.cpu.data 238 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::total 1085 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_miss_latency::.cpu.inst 83631000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::.cpu.data 24241000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::total 107872000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_accesses::.cpu.inst 993 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::.cpu.data 312 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::total 1305 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_miss_rate::.cpu.inst 0.852971 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::.cpu.data 0.762821 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::total 0.831418 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.inst 98737.898465 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.data 101852.941176 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::total 99421.198157 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_mshr_misses::.cpu.inst 847 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::.cpu.data 238 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::total 1085 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.inst 66691000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.data 19481000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::total 86172000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.inst 0.852971 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.data 0.762821 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.831418 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.inst 78737.898465 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 81852.941176 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79421.198157 # average ReadSharedReq mshr miss latency system.l2cache.InvalidateReq_misses::.cpu.data 8 # number of InvalidateReq misses system.l2cache.InvalidateReq_misses::total 8 # number of InvalidateReq misses system.l2cache.InvalidateReq_accesses::.cpu.data 8 # number of InvalidateReq accesses(hits+misses) system.l2cache.InvalidateReq_accesses::total 8 # number of InvalidateReq accesses(hits+misses) system.l2cache.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_mshr_misses::.cpu.data 8 # number of InvalidateReq MSHR misses system.l2cache.InvalidateReq_mshr_misses::total 8 # number of InvalidateReq MSHR misses system.l2cache.InvalidateReq_mshr_miss_latency::.cpu.data 232000 # number of InvalidateReq MSHR miss cycles system.l2cache.InvalidateReq_mshr_miss_latency::total 232000 # number of InvalidateReq MSHR miss cycles system.l2cache.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_avg_mshr_miss_latency::.cpu.data 29000 # average InvalidateReq mshr miss latency system.l2cache.InvalidateReq_avg_mshr_miss_latency::total 29000 # average InvalidateReq mshr miss latency system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.l2cache.tags.tagsinuse 4089.781196 # Cycle average of tags in use system.l2cache.tags.total_refs 22355 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 7500 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 2.980667 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 86000 # Cycle when the warmup percentage was hit. system.l2cache.tags.occ_blocks::.writebacks 1.027755 # Average occupied blocks per requestor system.l2cache.tags.occ_blocks::.cpu.inst 89.872198 # Average occupied blocks per requestor system.l2cache.tags.occ_blocks::.cpu.data 3998.881243 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::.writebacks 0.000251 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::.cpu.inst 0.021941 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::.cpu.data 0.976289 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.998482 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::4 4096 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 186644 # Number of tag accesses system.l2cache.tags.data_accesses 186644 # Number of data accesses system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 463987630000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::.cpu.inst 54208 # Number of bytes read from this memory system.mem_ctrl.bytes_read::.cpu.data 425280 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 479488 # Number of bytes read from this memory system.mem_ctrl.bytes_inst_read::.cpu.inst 54208 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_inst_read::total 54208 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_written::.writebacks 158720 # Number of bytes written to this memory system.mem_ctrl.bytes_written::total 158720 # Number of bytes written to this memory system.mem_ctrl.num_reads::.cpu.inst 847 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::.cpu.data 6645 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 7492 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::.writebacks 2480 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 2480 # Number of write requests responded to by this memory system.mem_ctrl.bw_read::.cpu.inst 116831 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::.cpu.data 916576 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::total 1033407 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::.cpu.inst 116831 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::total 116831 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_write::.writebacks 342078 # Write bandwidth from this memory (bytes/s) system.mem_ctrl.bw_write::total 342078 # Write bandwidth from this memory (bytes/s) system.mem_ctrl.bw_total::.writebacks 342078 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.inst 116831 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.data 916576 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::total 1375485 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.avgPriority_.writebacks::samples 2480.00 # Average QoS priority value for accepted requests system.mem_ctrl.avgPriority_.cpu.inst::samples 847.00 # Average QoS priority value for accepted requests system.mem_ctrl.avgPriority_.cpu.data::samples 6645.00 # Average QoS priority value for accepted requests system.mem_ctrl.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) system.mem_ctrl.priorityMaxLatency 0.002769804500 # per QoS priority maximum request to response latency (s) system.mem_ctrl.numReadWriteTurnArounds 137 # Number of turnarounds from READ to WRITE system.mem_ctrl.numWriteReadTurnArounds 137 # Number of turnarounds from WRITE to READ system.mem_ctrl.numStayReadState 136629 # Number of times bus staying in READ state system.mem_ctrl.numStayWriteState 2321 # Number of times bus staying in WRITE state system.mem_ctrl.readReqs 7492 # Number of read requests accepted system.mem_ctrl.writeReqs 2480 # Number of write requests accepted system.mem_ctrl.readBursts 7492 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 2480 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 545 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 519 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 466 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 403 # Per bank write bursts system.mem_ctrl.perBankRdBursts::4 395 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 421 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 445 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 448 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 427 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 464 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 452 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 508 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 521 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 545 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 453 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 480 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 157 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 146 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 145 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 165 # Per bank write bursts system.mem_ctrl.perBankWrBursts::4 177 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 161 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 151 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 135 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 134 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 133 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 134 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 160 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 199 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 218 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 128 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 115 # Per bank write bursts system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 21.91 # Average write queue length when enqueuing system.mem_ctrl.totQLat 47057500 # Total ticks spent queuing system.mem_ctrl.totBusLat 37460000 # Total ticks spent in databus transfers system.mem_ctrl.totMemAccLat 187532500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.avgQLat 6281.03 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrl.avgMemAccLat 25031.03 # Average memory access latency per DRAM burst system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrl.readRowHits 6581 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 2138 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 87.84 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate 86.21 # Row buffer hit rate for writes system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::6 7492 # Read request sizes (log2) system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 2480 # Write request sizes (log2) system.mem_ctrl.rdQLenPdf::0 7489 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 3 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 134 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 134 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::17 138 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::18 138 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 138 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 138 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 138 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::22 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::26 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::27 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::28 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::29 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::32 137 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 1231 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::mean 517.303006 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::gmean 340.660945 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::stdev 382.346786 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::0-127 202 16.41% 16.41% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::128-255 239 19.42% 35.82% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::256-383 130 10.56% 46.39% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::384-511 67 5.44% 51.83% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::512-639 74 6.01% 57.84% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 54 4.39% 62.23% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 97 7.88% 70.11% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::896-1023 57 4.63% 74.74% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 311 25.26% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 1231 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 137 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::mean 54.649635 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::gmean 20.866224 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::stdev 384.353230 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::0-255 136 99.27% 99.27% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::4352-4607 1 0.73% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 137 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 137 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 17.941606 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 17.938206 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::stdev 0.337953 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 4 2.92% 2.92% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::18 133 97.08% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 137 # Writes before turning the bus around for reads system.mem_ctrl.bytesReadDRAM 479488 # Total number of bytes read from DRAM system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 157312 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 479488 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 158720 # Total written bytes from the system interface side system.mem_ctrl.avgRdBW 1.03 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.34 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 1.03 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.34 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 0.01 # Data bus utilization in percentage system.mem_ctrl.busUtilRead 0.01 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.totGap 4121222000 # Total gap between requests system.mem_ctrl.avgGap 413279.38 # Average gap between requests system.mem_ctrl.masterReadBytes::.cpu.inst 54208 # Per-master bytes read from memory system.mem_ctrl.masterReadBytes::.cpu.data 425280 # Per-master bytes read from memory system.mem_ctrl.masterWriteBytes::.writebacks 157312 # Per-master bytes write to memory system.mem_ctrl.masterReadRate::.cpu.inst 116830.700852951617 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterReadRate::.cpu.data 916576.159584254492 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterWriteRate::.writebacks 339043.521483536111 # Per-master bytes write to memory rate (Bytes/sec) system.mem_ctrl.masterReadAccesses::.cpu.inst 847 # Per-master read serviced memory accesses system.mem_ctrl.masterReadAccesses::.cpu.data 6645 # Per-master read serviced memory accesses system.mem_ctrl.masterWriteAccesses::.writebacks 2480 # Per-master write serviced memory accesses system.mem_ctrl.masterReadTotalLat::.cpu.inst 23215250 # Per-master read total memory access latency system.mem_ctrl.masterReadTotalLat::.cpu.data 164317250 # Per-master read total memory access latency system.mem_ctrl.masterWriteTotalLat::.writebacks 48147267000 # Per-master write total memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.inst 27408.80 # Per-master read average memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.data 24727.95 # Per-master read average memory access latency system.mem_ctrl.masterWriteAvgLat::.writebacks 19414220.56 # Per-master write average memory access latency system.mem_ctrl.pageHitRate 87.43 # Row buffer hit rate, read and write combined system.mem_ctrl.rank1.actEnergy 4441080 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank1.preEnergy 2360490 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank1.readEnergy 27489000 # Energy for read commands per rank (pJ) system.mem_ctrl.rank1.writeEnergy 6373620 # Energy for write commands per rank (pJ) system.mem_ctrl.rank1.refreshEnergy 36626397600.000008 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank1.actBackEnergy 7107059250 # Energy for active background per rank (pJ) system.mem_ctrl.rank1.preBackEnergy 172186357920 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank1.totalEnergy 215960478960 # Total energy per rank (pJ) system.mem_ctrl.rank1.averagePower 465.444475 # Core power per rank (mW) system.mem_ctrl.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank1.memoryStateTime::IDLE 447578937250 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::REF 15493400000 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::ACT 915292750 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl.rank0.actEnergy 4348260 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank0.preEnergy 2311155 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank0.readEnergy 26003880 # Energy for read commands per rank (pJ) system.mem_ctrl.rank0.writeEnergy 6457140 # Energy for write commands per rank (pJ) system.mem_ctrl.rank0.refreshEnergy 36626397600.000008 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank0.actBackEnergy 7081334580 # Energy for active background per rank (pJ) system.mem_ctrl.rank0.preBackEnergy 172208020800 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank0.totalEnergy 215954873415 # Total energy per rank (pJ) system.mem_ctrl.rank0.averagePower 465.432394 # Core power per rank (mW) system.mem_ctrl.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank0.memoryStateTime::IDLE 447635350750 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::REF 15493400000 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT 858879250 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states ---------- End Simulation Statistics ----------