---------- Begin Simulation Statistics ---------- final_tick 57109972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 1187425 # Simulator instruction rate (inst/s) host_mem_usage 803512 # Number of bytes of host memory used host_op_rate 1189940 # Simulator op (including micro ops) rate (op/s) host_seconds 16.99 # Real time elapsed on the host host_tick_rate 3361090020 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 20175987 # Number of instructions simulated sim_ops 20218844 # Number of ops (including micro ops) simulated sim_seconds 0.057110 # Number of seconds simulated sim_ticks 57109972000 # Number of ticks simulated system.cpu.Branches 2823737 # Number of branches fetched system.cpu.committedInsts 20175987 # Number of instructions committed system.cpu.committedOps 20218844 # Number of ops (including micro ops) committed system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.numCycles 57109972 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 57109971.999000 # Number of busy cycles system.cpu.num_cc_register_reads 8464944 # number of times the CC registers were read system.cpu.num_cc_register_writes 8496899 # number of times the CC registers were written system.cpu.num_conditional_control_insts 2820095 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_func_calls 3078 # number of times a function call or return occured system.cpu.num_idle_cycles 0.001000 # Number of idle cycles system.cpu.num_int_alu_accesses 15038795 # Number of integer alu accesses system.cpu.num_int_insts 15038795 # number of integer instructions system.cpu.num_int_register_reads 44770040 # number of times the integer registers were read system.cpu.num_int_register_writes 10552398 # number of times the integer registers were written system.cpu.num_load_insts 5096203 # Number of load instructions system.cpu.num_mem_refs 7318143 # number of memory refs system.cpu.num_store_insts 2221940 # Number of store instructions system.cpu.num_vec_alu_accesses 9044105 # Number of vector alu accesses system.cpu.num_vec_insts 9044105 # number of vector instructions system.cpu.num_vec_register_reads 8814729 # number of times the vector registers were read system.cpu.num_vec_register_writes 6881310 # number of times the vector registers were written system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 10377533 51.33% 51.33% # Class of executed instruction system.cpu.op_class::IntMult 131103 0.65% 51.97% # Class of executed instruction system.cpu.op_class::IntDiv 3 0.00% 51.97% # Class of executed instruction system.cpu.op_class::FloatAdd 32768 0.16% 52.14% # Class of executed instruction system.cpu.op_class::FloatCmp 32768 0.16% 52.30% # Class of executed instruction system.cpu.op_class::FloatCvt 65536 0.32% 52.62% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 52.62% # Class of executed instruction system.cpu.op_class::FloatMultAcc 2162688 10.70% 63.32% # Class of executed instruction system.cpu.op_class::FloatDiv 32768 0.16% 63.48% # Class of executed instruction system.cpu.op_class::FloatMisc 32772 0.16% 63.64% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.64% # Class of executed instruction system.cpu.op_class::SimdAdd 5 0.00% 63.64% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.64% # Class of executed instruction system.cpu.op_class::SimdAlu 4 0.00% 63.64% # Class of executed instruction system.cpu.op_class::SimdCmp 4 0.00% 63.64% # Class of executed instruction system.cpu.op_class::SimdCvt 0 0.00% 63.64% # Class of executed instruction system.cpu.op_class::SimdMisc 32775 0.16% 63.81% # Class of executed instruction system.cpu.op_class::SimdMult 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdMultAcc 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdShift 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdShiftAcc 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdDiv 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdSqrt 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatAdd 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatAlu 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdReduceAdd 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdReduceAlu 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdReduceCmp 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatReduceAdd 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdFloatReduceCmp 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdAes 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdAesMix 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdSha1Hash 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdSha1Hash2 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdSha256Hash 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdSha256Hash2 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdShaSigma2 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdShaSigma3 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::SimdPredAlu 0 0.00% 63.81% # Class of executed instruction system.cpu.op_class::MemRead 5096203 25.21% 89.01% # Class of executed instruction system.cpu.op_class::MemWrite 2221940 10.99% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 20218871 # Class of executed instruction system.cpu.workload.numSyscalls 26 # Number of system calls system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_single_requests 48130 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_single_snoops 289 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.tot_requests 97540 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.tot_snoops 289 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 7964 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 20203 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 5819 # Transaction distribution system.membus.trans_dist::WritebackDirty 6014 # Transaction distribution system.membus.trans_dist::CleanEvict 1950 # Transaction distribution system.membus.trans_dist::ReadExReq 6412 # Transaction distribution system.membus.trans_dist::ReadExResp 6412 # Transaction distribution system.membus.trans_dist::ReadSharedReq 5819 # Transaction distribution system.membus.trans_dist::InvalidateReq 8 # Transaction distribution system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 32434 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 32434 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 1167680 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 1167680 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 12239 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 12239 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 12239 # Request fanout histogram system.membus.reqLayer0.occupancy 44259000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer0.occupancy 64896500 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.1 # Layer utilization (%) system.l2bus.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 38872 # Transaction distribution system.l2bus.trans_dist::WritebackDirty 37650 # Transaction distribution system.l2bus.trans_dist::CleanEvict 18625 # Transaction distribution system.l2bus.trans_dist::ReadExReq 10530 # Transaction distribution system.l2bus.trans_dist::ReadExResp 10530 # Transaction distribution system.l2bus.trans_dist::ReadSharedReq 38872 # Transaction distribution system.l2bus.trans_dist::InvalidateReq 8 # Transaction distribution system.l2bus.trans_dist::InvalidateResp 8 # Transaction distribution system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 2978 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 143972 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count::total 146950 # Packet count per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 68992 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 5117440 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 5186432 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 8145 # Total snoops (count) system.l2bus.snoopTraffic 384896 # Total snoop traffic (bytes) system.l2bus.snoop_fanout::samples 57555 # Request fanout histogram system.l2bus.snoop_fanout::mean 0.005039 # Request fanout histogram system.l2bus.snoop_fanout::stdev 0.070805 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.l2bus.snoop_fanout::0 57265 99.50% 99.50% # Request fanout histogram system.l2bus.snoop_fanout::1 290 0.50% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 57555 # Request fanout histogram system.l2bus.respLayer1.occupancy 144980000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.3 # Layer utilization (%) system.l2bus.reqLayer0.occupancy 160812000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.l2bus.respLayer0.occupancy 3234000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 0.0 # Layer utilization (%) system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.cpu.numPwrStateTransitions 1 # Number of power state transitions system.cpu.pwrStateResidencyTicks::ON 57109972000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 20174936 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 20174936 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 20174936 # number of overall hits system.cpu.icache.overall_hits::total 20174936 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 1078 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1078 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 1078 # number of overall misses system.cpu.icache.overall_misses::total 1078 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 99986000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 99986000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 99986000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 99986000 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 20176014 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 20176014 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 20176014 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 20176014 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 92751.391466 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 92751.391466 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 92751.391466 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 92751.391466 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.demand_mshr_misses::.cpu.inst 1078 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 1078 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 97830000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 97830000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 97830000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 97830000 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 90751.391466 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 90751.391466 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 90751.391466 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 90751.391466 # average overall mshr miss latency system.cpu.icache.replacements 822 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 20174936 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 20174936 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 1078 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1078 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 99986000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 99986000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 20176014 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 20176014 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 92751.391466 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 92751.391466 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 1078 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 97830000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 97830000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 90751.391466 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90751.391466 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 255.764869 # Cycle average of tags in use system.cpu.icache.tags.total_refs 20176014 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1078 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18716.153989 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 107000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 255.764869 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.999082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 178 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 40353106 # Number of tag accesses system.cpu.icache.tags.data_accesses 40353106 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 7269701 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 7269701 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 7269708 # number of overall hits system.cpu.dcache.overall_hits::total 7269708 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 48328 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 48328 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 48336 # number of overall misses system.cpu.dcache.overall_misses::total 48336 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 2120367000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 2120367000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 2120367000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 2120367000 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 7318029 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 7318029 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 7318044 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 7318044 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.006604 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.006604 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.006605 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006605 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 43874.503393 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 43874.503393 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 43867.241807 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 43867.241807 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::.writebacks 31636 # number of writebacks system.cpu.dcache.writebacks::total 31636 # number of writebacks system.cpu.dcache.demand_mshr_hits::.cpu.data 5 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::.cpu.data 5 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses::.cpu.data 48323 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 48323 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 48331 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 48331 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 2023242000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 2023242000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 2024126000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 2024126000 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.006603 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006603 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.006604 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006604 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 41869.130642 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 41869.130642 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 41880.490782 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 41880.490782 # average overall mshr miss latency system.cpu.dcache.replacements 47308 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 5058398 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 5058398 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 37790 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 37790 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 1365834000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 1365834000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 5096188 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 5096188 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.007415 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007415 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 36142.736174 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 36142.736174 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 5 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 37785 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 37785 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 1289785000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 1289785000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.007414 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007414 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 34134.841868 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34134.841868 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 2211303 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 2211303 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 10530 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 10530 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 754101000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 754101000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 2221833 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 2221833 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.004739 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.004739 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 71614.529915 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 71614.529915 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 10530 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 10530 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 733041000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 733041000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.004739 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004739 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 69614.529915 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69614.529915 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_hits::.cpu.data 7 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 7 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_misses::.cpu.data 8 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_accesses::.cpu.data 15 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 15 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.533333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.533333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 8 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 8 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 884000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 884000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.533333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.533333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 110500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 110500 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_misses::.cpu.data 8 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 8 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 432000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 432000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_accesses::.cpu.data 8 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 8 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 54000 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 54000 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 8 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 8 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 416000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 416000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 52000 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 52000 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 103 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 103 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 123000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 123000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 104 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 104 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.009615 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.009615 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 123000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 123000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 121000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 121000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.009615 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.009615 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 121000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 121000 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_hits::.cpu.data 104 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 104 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 104 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 104 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 1019.767198 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 7318247 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 48332 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 151.416184 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 236000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 1019.767198 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.995866 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995866 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 391 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 14684836 # Number of tag accesses system.cpu.dcache.tags.data_accesses 14684836 # Number of data accesses system.l2cache.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.l2cache.demand_hits::.cpu.inst 146 # number of demand (read+write) hits system.l2cache.demand_hits::.cpu.data 37025 # number of demand (read+write) hits system.l2cache.demand_hits::total 37171 # number of demand (read+write) hits system.l2cache.overall_hits::.cpu.inst 146 # number of overall hits system.l2cache.overall_hits::.cpu.data 37025 # number of overall hits system.l2cache.overall_hits::total 37171 # number of overall hits system.l2cache.demand_misses::.cpu.inst 932 # number of demand (read+write) misses system.l2cache.demand_misses::.cpu.data 11299 # number of demand (read+write) misses system.l2cache.demand_misses::total 12231 # number of demand (read+write) misses system.l2cache.overall_misses::.cpu.inst 932 # number of overall misses system.l2cache.overall_misses::.cpu.data 11299 # number of overall misses system.l2cache.overall_misses::total 12231 # number of overall misses system.l2cache.demand_miss_latency::.cpu.inst 91519000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::.cpu.data 1101333000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::total 1192852000 # number of demand (read+write) miss cycles system.l2cache.overall_miss_latency::.cpu.inst 91519000 # number of overall miss cycles system.l2cache.overall_miss_latency::.cpu.data 1101333000 # number of overall miss cycles system.l2cache.overall_miss_latency::total 1192852000 # number of overall miss cycles system.l2cache.demand_accesses::.cpu.inst 1078 # number of demand (read+write) accesses system.l2cache.demand_accesses::.cpu.data 48324 # number of demand (read+write) accesses system.l2cache.demand_accesses::total 49402 # number of demand (read+write) accesses system.l2cache.overall_accesses::.cpu.inst 1078 # number of overall (read+write) accesses system.l2cache.overall_accesses::.cpu.data 48324 # number of overall (read+write) accesses system.l2cache.overall_accesses::total 49402 # number of overall (read+write) accesses system.l2cache.demand_miss_rate::.cpu.inst 0.864564 # miss rate for demand accesses system.l2cache.demand_miss_rate::.cpu.data 0.233818 # miss rate for demand accesses system.l2cache.demand_miss_rate::total 0.247581 # miss rate for demand accesses system.l2cache.overall_miss_rate::.cpu.inst 0.864564 # miss rate for overall accesses system.l2cache.overall_miss_rate::.cpu.data 0.233818 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.247581 # miss rate for overall accesses system.l2cache.demand_avg_miss_latency::.cpu.inst 98196.351931 # average overall miss latency system.l2cache.demand_avg_miss_latency::.cpu.data 97471.723161 # average overall miss latency system.l2cache.demand_avg_miss_latency::total 97526.939743 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.inst 98196.351931 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.data 97471.723161 # average overall miss latency system.l2cache.overall_avg_miss_latency::total 97526.939743 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2cache.writebacks::.writebacks 6014 # number of writebacks system.l2cache.writebacks::total 6014 # number of writebacks system.l2cache.demand_mshr_misses::.cpu.inst 932 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::.cpu.data 11299 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::total 12231 # number of demand (read+write) MSHR misses system.l2cache.overall_mshr_misses::.cpu.inst 932 # number of overall MSHR misses system.l2cache.overall_mshr_misses::.cpu.data 11299 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 12231 # number of overall MSHR misses system.l2cache.demand_mshr_miss_latency::.cpu.inst 72879000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::.cpu.data 875353000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::total 948232000 # number of demand (read+write) MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.inst 72879000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.data 875353000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::total 948232000 # number of overall MSHR miss cycles system.l2cache.demand_mshr_miss_rate::.cpu.inst 0.864564 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::.cpu.data 0.233818 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::total 0.247581 # mshr miss rate for demand accesses system.l2cache.overall_mshr_miss_rate::.cpu.inst 0.864564 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::.cpu.data 0.233818 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.247581 # mshr miss rate for overall accesses system.l2cache.demand_avg_mshr_miss_latency::.cpu.inst 78196.351931 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::.cpu.data 77471.723161 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::total 77526.939743 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.inst 78196.351931 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.data 77471.723161 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 77526.939743 # average overall mshr miss latency system.l2cache.replacements 8145 # number of replacements system.l2cache.WritebackDirty_hits::.writebacks 31636 # number of WritebackDirty hits system.l2cache.WritebackDirty_hits::total 31636 # number of WritebackDirty hits system.l2cache.WritebackDirty_accesses::.writebacks 31636 # number of WritebackDirty accesses(hits+misses) system.l2cache.WritebackDirty_accesses::total 31636 # number of WritebackDirty accesses(hits+misses) system.l2cache.CleanEvict_mshr_misses::.writebacks 109 # number of CleanEvict MSHR misses system.l2cache.CleanEvict_mshr_misses::total 109 # number of CleanEvict MSHR misses system.l2cache.CleanEvict_mshr_miss_rate::.writebacks inf # mshr miss rate for CleanEvict accesses system.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2cache.ReadExReq_hits::.cpu.data 4118 # number of ReadExReq hits system.l2cache.ReadExReq_hits::total 4118 # number of ReadExReq hits system.l2cache.ReadExReq_misses::.cpu.data 6412 # number of ReadExReq misses system.l2cache.ReadExReq_misses::total 6412 # number of ReadExReq misses system.l2cache.ReadExReq_miss_latency::.cpu.data 614973000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_miss_latency::total 614973000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_accesses::.cpu.data 10530 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 10530 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_miss_rate::.cpu.data 0.608927 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_miss_rate::total 0.608927 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_miss_latency::.cpu.data 95909.700561 # average ReadExReq miss latency system.l2cache.ReadExReq_avg_miss_latency::total 95909.700561 # average ReadExReq miss latency system.l2cache.ReadExReq_mshr_misses::.cpu.data 6412 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 6412 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_miss_latency::.cpu.data 486733000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_latency::total 486733000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::.cpu.data 0.608927 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 0.608927 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_mshr_miss_latency::.cpu.data 75909.700561 # average ReadExReq mshr miss latency system.l2cache.ReadExReq_avg_mshr_miss_latency::total 75909.700561 # average ReadExReq mshr miss latency system.l2cache.ReadSharedReq_hits::.cpu.inst 146 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::.cpu.data 32907 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 33053 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_misses::.cpu.inst 932 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::.cpu.data 4887 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::total 5819 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_miss_latency::.cpu.inst 91519000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::.cpu.data 486360000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::total 577879000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_accesses::.cpu.inst 1078 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::.cpu.data 37794 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::total 38872 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_miss_rate::.cpu.inst 0.864564 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::.cpu.data 0.129306 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::total 0.149696 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.inst 98196.351931 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.data 99521.178637 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::total 99308.987799 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_mshr_misses::.cpu.inst 932 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::.cpu.data 4887 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::total 5819 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.inst 72879000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.data 388620000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::total 461499000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.inst 0.864564 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.data 0.129306 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.149696 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.inst 78196.351931 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 79521.178637 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79308.987799 # average ReadSharedReq mshr miss latency system.l2cache.InvalidateReq_misses::.cpu.data 8 # number of InvalidateReq misses system.l2cache.InvalidateReq_misses::total 8 # number of InvalidateReq misses system.l2cache.InvalidateReq_accesses::.cpu.data 8 # number of InvalidateReq accesses(hits+misses) system.l2cache.InvalidateReq_accesses::total 8 # number of InvalidateReq accesses(hits+misses) system.l2cache.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_mshr_misses::.cpu.data 8 # number of InvalidateReq MSHR misses system.l2cache.InvalidateReq_mshr_misses::total 8 # number of InvalidateReq MSHR misses system.l2cache.InvalidateReq_mshr_miss_latency::.cpu.data 232000 # number of InvalidateReq MSHR miss cycles system.l2cache.InvalidateReq_mshr_miss_latency::total 232000 # number of InvalidateReq MSHR miss cycles system.l2cache.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_avg_mshr_miss_latency::.cpu.data 29000 # average InvalidateReq mshr miss latency system.l2cache.InvalidateReq_avg_mshr_miss_latency::total 29000 # average InvalidateReq mshr miss latency system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.l2cache.tags.tagsinuse 4045.503022 # Cycle average of tags in use system.l2cache.tags.total_refs 97422 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 12241 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 7.958664 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 86000 # Cycle when the warmup percentage was hit. system.l2cache.tags.occ_blocks::.writebacks 1.964999 # Average occupied blocks per requestor system.l2cache.tags.occ_blocks::.cpu.inst 31.852167 # Average occupied blocks per requestor system.l2cache.tags.occ_blocks::.cpu.data 4011.685856 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::.writebacks 0.000480 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::.cpu.inst 0.007776 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::.cpu.data 0.979415 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.987672 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::4 3160 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 792553 # Number of tag accesses system.l2cache.tags.data_accesses 792553 # Number of data accesses system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 57109972000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::.cpu.inst 59648 # Number of bytes read from this memory system.mem_ctrl.bytes_read::.cpu.data 723136 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 782784 # Number of bytes read from this memory system.mem_ctrl.bytes_inst_read::.cpu.inst 59648 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_inst_read::total 59648 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_written::.writebacks 384896 # Number of bytes written to this memory system.mem_ctrl.bytes_written::total 384896 # Number of bytes written to this memory system.mem_ctrl.num_reads::.cpu.inst 932 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::.cpu.data 11299 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 12231 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::.writebacks 6014 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 6014 # Number of write requests responded to by this memory system.mem_ctrl.bw_read::.cpu.inst 1044441 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::.cpu.data 12662167 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::total 13706608 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::.cpu.inst 1044441 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::total 1044441 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_write::.writebacks 6739559 # Write bandwidth from this memory (bytes/s) system.mem_ctrl.bw_write::total 6739559 # Write bandwidth from this memory (bytes/s) system.mem_ctrl.bw_total::.writebacks 6739559 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.inst 1044441 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.data 12662167 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::total 20446167 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.avgPriority_.writebacks::samples 6014.00 # Average QoS priority value for accepted requests system.mem_ctrl.avgPriority_.cpu.inst::samples 932.00 # Average QoS priority value for accepted requests system.mem_ctrl.avgPriority_.cpu.data::samples 11299.00 # Average QoS priority value for accepted requests system.mem_ctrl.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) system.mem_ctrl.priorityMaxLatency 0.006282636500 # per QoS priority maximum request to response latency (s) system.mem_ctrl.numReadWriteTurnArounds 334 # Number of turnarounds from READ to WRITE system.mem_ctrl.numWriteReadTurnArounds 334 # Number of turnarounds from WRITE to READ system.mem_ctrl.numStayReadState 45111 # Number of times bus staying in READ state system.mem_ctrl.numStayWriteState 5659 # Number of times bus staying in WRITE state system.mem_ctrl.readReqs 12231 # Number of read requests accepted system.mem_ctrl.writeReqs 6014 # Number of write requests accepted system.mem_ctrl.readBursts 12231 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 6014 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 862 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 809 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 795 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 638 # Per bank write bursts system.mem_ctrl.perBankRdBursts::4 586 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 587 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 715 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 790 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 742 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 761 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 810 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 873 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 836 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 830 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 776 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 821 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 335 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 298 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 342 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 295 # Per bank write bursts system.mem_ctrl.perBankWrBursts::4 319 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 291 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 395 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 464 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 437 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 418 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 463 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 465 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 415 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 387 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 325 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 338 # Per bank write bursts system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 23.97 # Average write queue length when enqueuing system.mem_ctrl.totQLat 91377250 # Total ticks spent queuing system.mem_ctrl.totBusLat 61155000 # Total ticks spent in databus transfers system.mem_ctrl.totMemAccLat 320708500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.avgQLat 7470.95 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrl.avgMemAccLat 26220.95 # Average memory access latency per DRAM burst system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrl.readRowHits 9484 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 5230 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 77.54 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate 86.96 # Row buffer hit rate for writes system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::6 12231 # Read request sizes (log2) system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 6014 # Write request sizes (log2) system.mem_ctrl.rdQLenPdf::0 12228 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 3 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 322 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 322 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::17 335 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::18 335 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 335 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 336 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 335 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::22 335 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 335 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 335 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 335 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::26 335 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::27 334 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::28 334 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::29 334 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 334 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 334 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::32 334 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 3494 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::mean 333.115054 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::gmean 214.666864 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::stdev 327.422914 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::0-127 749 21.44% 21.44% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::128-255 1222 34.97% 56.41% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::256-383 583 16.69% 73.10% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::384-511 149 4.26% 77.36% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::512-639 83 2.38% 79.74% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 78 2.23% 81.97% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 111 3.18% 85.15% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::896-1023 64 1.83% 86.98% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 455 13.02% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 3494 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 334 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::mean 36.497006 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::gmean 20.634292 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::stdev 246.720627 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::0-255 333 99.70% 99.70% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::4352-4607 1 0.30% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 334 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 334 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 17.925150 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 17.920571 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::stdev 0.391842 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 13 3.89% 3.89% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::18 320 95.81% 99.70% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::19 1 0.30% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 334 # Writes before turning the bus around for reads system.mem_ctrl.bytesReadDRAM 782784 # Total number of bytes read from DRAM system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 383168 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 782784 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 384896 # Total written bytes from the system interface side system.mem_ctrl.avgRdBW 13.71 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 6.71 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 13.71 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 6.74 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 0.16 # Data bus utilization in percentage system.mem_ctrl.busUtilRead 0.11 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.mem_ctrl.totGap 57109877000 # Total gap between requests system.mem_ctrl.avgGap 3130165.91 # Average gap between requests system.mem_ctrl.masterReadBytes::.cpu.inst 59648 # Per-master bytes read from memory system.mem_ctrl.masterReadBytes::.cpu.data 723136 # Per-master bytes read from memory system.mem_ctrl.masterWriteBytes::.writebacks 383168 # Per-master bytes write to memory system.mem_ctrl.masterReadRate::.cpu.inst 1044441.065388720483 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterReadRate::.cpu.data 12662166.950458317995 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterWriteRate::.writebacks 6709301.135710589588 # Per-master bytes write to memory rate (Bytes/sec) system.mem_ctrl.masterReadAccesses::.cpu.inst 932 # Per-master read serviced memory accesses system.mem_ctrl.masterReadAccesses::.cpu.data 11299 # Per-master read serviced memory accesses system.mem_ctrl.masterWriteAccesses::.writebacks 6014 # Per-master write serviced memory accesses system.mem_ctrl.masterReadTotalLat::.cpu.inst 25035500 # Per-master read total memory access latency system.mem_ctrl.masterReadTotalLat::.cpu.data 295673000 # Per-master read total memory access latency system.mem_ctrl.masterWriteTotalLat::.writebacks 1332377906250 # Per-master write total memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.inst 26862.12 # Per-master read average memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.data 26168.07 # Per-master read average memory access latency system.mem_ctrl.masterWriteAvgLat::.writebacks 221546043.61 # Per-master write average memory access latency system.mem_ctrl.pageHitRate 80.65 # Row buffer hit rate, read and write combined system.mem_ctrl.rank1.actEnergy 13273260 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank1.preEnergy 7035930 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank1.readEnergy 46045860 # Energy for read commands per rank (pJ) system.mem_ctrl.rank1.writeEnergy 16954560 # Energy for write commands per rank (pJ) system.mem_ctrl.rank1.refreshEnergy 4507769760.000001 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank1.actBackEnergy 3129403170 # Energy for active background per rank (pJ) system.mem_ctrl.rank1.preBackEnergy 19294942560 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank1.totalEnergy 27015425100 # Total energy per rank (pJ) system.mem_ctrl.rank1.averagePower 473.042170 # Core power per rank (mW) system.mem_ctrl.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank1.memoryStateTime::IDLE 50131658000 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::REF 1906840000 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::ACT 5071474000 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl.rank0.actEnergy 11745300 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank0.preEnergy 6223800 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank0.readEnergy 41283480 # Energy for read commands per rank (pJ) system.mem_ctrl.rank0.writeEnergy 14297580 # Energy for write commands per rank (pJ) system.mem_ctrl.rank0.refreshEnergy 4507769760.000001 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank0.actBackEnergy 2808595200 # Energy for active background per rank (pJ) system.mem_ctrl.rank0.preBackEnergy 19565096640 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank0.totalEnergy 26955011760 # Total energy per rank (pJ) system.mem_ctrl.rank0.averagePower 471.984328 # Core power per rank (mW) system.mem_ctrl.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank0.memoryStateTime::IDLE 50837118500 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::REF 1906840000 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT 4366013500 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states ---------- End Simulation Statistics ----------