---------- Begin Simulation Statistics ---------- final_tick 97881415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 758280 # Simulator instruction rate (inst/s) host_mem_usage 803608 # Number of bytes of host memory used host_op_rate 857636 # Simulator op (including micro ops) rate (op/s) host_seconds 21.54 # Real time elapsed on the host host_tick_rate 4544787694 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 16331011 # Number of instructions simulated sim_ops 18470947 # Number of ops (including micro ops) simulated sim_seconds 0.097881 # Number of seconds simulated sim_ticks 97881415000 # Number of ticks simulated system.cpu.Branches 2258110 # Number of branches fetched system.cpu.committedInsts 16331011 # Number of instructions committed system.cpu.committedOps 18470947 # Number of ops (including micro ops) committed system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.numCycles 97881415 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 97881414.999000 # Number of busy cycles system.cpu.num_cc_register_reads 6755103 # number of times the CC registers were read system.cpu.num_cc_register_writes 6787061 # number of times the CC registers were written system.cpu.num_conditional_control_insts 2254498 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_func_calls 3056 # number of times a function call or return occured system.cpu.num_idle_cycles 0.001000 # Number of idle cycles system.cpu.num_int_alu_accesses 13893208 # Number of integer alu accesses system.cpu.num_int_insts 13893208 # number of integer instructions system.cpu.num_int_register_reads 38814320 # number of times the integer registers were read system.cpu.num_int_register_writes 9652711 # number of times the integer registers were written system.cpu.num_load_insts 4354133 # Number of load instructions system.cpu.num_mem_refs 6575954 # number of memory refs system.cpu.num_store_insts 2221821 # Number of store instructions system.cpu.num_vec_alu_accesses 8798345 # Number of vector alu accesses system.cpu.num_vec_insts 8798345 # number of vector instructions system.cpu.num_vec_register_reads 8814729 # number of times the vector registers were read system.cpu.num_vec_register_writes 6635550 # number of times the vector registers were written system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 9371831 50.74% 50.74% # Class of executed instruction system.cpu.op_class::IntMult 131097 0.71% 51.45% # Class of executed instruction system.cpu.op_class::IntDiv 3 0.00% 51.45% # Class of executed instruction system.cpu.op_class::FloatAdd 32768 0.18% 51.63% # Class of executed instruction system.cpu.op_class::FloatCmp 32768 0.18% 51.80% # Class of executed instruction system.cpu.op_class::FloatCvt 65536 0.35% 52.16% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 52.16% # Class of executed instruction system.cpu.op_class::FloatMultAcc 2162688 11.71% 63.87% # Class of executed instruction system.cpu.op_class::FloatDiv 32768 0.18% 64.04% # Class of executed instruction system.cpu.op_class::FloatMisc 32772 0.18% 64.22% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 64.22% # Class of executed instruction system.cpu.op_class::SimdAdd 5 0.00% 64.22% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 64.22% # Class of executed instruction system.cpu.op_class::SimdAlu 4 0.00% 64.22% # Class of executed instruction system.cpu.op_class::SimdCmp 4 0.00% 64.22% # Class of executed instruction system.cpu.op_class::SimdCvt 0 0.00% 64.22% # Class of executed instruction system.cpu.op_class::SimdMisc 32775 0.18% 64.40% # Class of executed instruction system.cpu.op_class::SimdMult 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdMultAcc 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdShift 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdShiftAcc 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdDiv 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdSqrt 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatAdd 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatAlu 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdReduceAdd 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdReduceAlu 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdReduceCmp 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatReduceAdd 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdFloatReduceCmp 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdAes 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdAesMix 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdSha1Hash 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdSha1Hash2 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdSha256Hash 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdSha256Hash2 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdShaSigma2 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdShaSigma3 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::SimdPredAlu 0 0.00% 64.40% # Class of executed instruction system.cpu.op_class::MemRead 4354133 23.57% 87.97% # Class of executed instruction system.cpu.op_class::MemWrite 2221821 12.03% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 18470974 # Class of executed instruction system.cpu.workload.numSyscalls 26 # Number of system calls system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_single_requests 2130540 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_single_snoops 298 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.tot_requests 4262360 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.tot_snoops 298 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 7608 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 19497 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 5469 # Transaction distribution system.membus.trans_dist::WritebackDirty 5675 # Transaction distribution system.membus.trans_dist::CleanEvict 1933 # Transaction distribution system.membus.trans_dist::ReadExReq 6412 # Transaction distribution system.membus.trans_dist::ReadExResp 6412 # Transaction distribution system.membus.trans_dist::ReadSharedReq 5469 # Transaction distribution system.membus.trans_dist::InvalidateReq 8 # Transaction distribution system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 31378 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31378 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 1123584 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 1123584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 11889 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 11889 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 11889 # Request fanout histogram system.membus.reqLayer0.occupancy 42197000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 63041500 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.1 # Layer utilization (%) system.l2bus.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 2121284 # Transaction distribution system.l2bus.trans_dist::WritebackDirty 1590430 # Transaction distribution system.l2bus.trans_dist::CleanEvict 547904 # Transaction distribution system.l2bus.trans_dist::ReadExReq 10528 # Transaction distribution system.l2bus.trans_dist::ReadExResp 10528 # Transaction distribution system.l2bus.trans_dist::ReadSharedReq 2121284 # Transaction distribution system.l2bus.trans_dist::InvalidateReq 8 # Transaction distribution system.l2bus.trans_dist::InvalidateResp 8 # Transaction distribution system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 2957 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 6391223 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count::total 6394180 # Packet count per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 68544 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 237791744 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 237860288 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 7794 # Total snoops (count) system.l2bus.snoopTraffic 363200 # Total snoop traffic (bytes) system.l2bus.snoop_fanout::samples 2139614 # Request fanout histogram system.l2bus.snoop_fanout::mean 0.000140 # Request fanout histogram system.l2bus.snoop_fanout::stdev 0.011821 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.l2bus.snoop_fanout::0 2139315 99.99% 99.99% # Request fanout histogram system.l2bus.snoop_fanout::1 299 0.01% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 2139614 # Request fanout histogram system.l2bus.respLayer1.occupancy 6392231000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 6.5 # Layer utilization (%) system.l2bus.reqLayer0.occupancy 7431870000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 7.6 # Layer utilization (%) system.l2bus.respLayer0.occupancy 3213000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 0.0 # Layer utilization (%) system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.cpu.numPwrStateTransitions 1 # Number of power state transitions system.cpu.pwrStateResidencyTicks::ON 97881415000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 16329967 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 16329967 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 16329967 # number of overall hits system.cpu.icache.overall_hits::total 16329967 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 1071 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1071 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 1071 # number of overall misses system.cpu.icache.overall_misses::total 1071 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 98683000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 98683000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 98683000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 98683000 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 16331038 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 16331038 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 16331038 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 16331038 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 92140.989729 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 92140.989729 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 92140.989729 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 92140.989729 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.demand_mshr_misses::.cpu.inst 1071 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1071 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 1071 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1071 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 96541000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 96541000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 96541000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 96541000 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 90140.989729 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 90140.989729 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 90140.989729 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 90140.989729 # average overall mshr miss latency system.cpu.icache.replacements 815 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 16329967 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 16329967 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 1071 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1071 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 98683000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 98683000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 16331038 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 16331038 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 92140.989729 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 92140.989729 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 1071 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1071 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 96541000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 96541000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 90140.989729 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90140.989729 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 255.825399 # Cycle average of tags in use system.cpu.icache.tags.total_refs 16331038 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1071 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15248.401494 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 107000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 255.825399 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.999318 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999318 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 184 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 32663147 # Number of tag accesses system.cpu.icache.tags.data_accesses 32663147 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 4445081 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 4445081 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 4445087 # number of overall hits system.cpu.dcache.overall_hits::total 4445087 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 2130746 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2130746 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 2130753 # number of overall misses system.cpu.dcache.overall_misses::total 2130753 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 56232314000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 56232314000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 56232314000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 56232314000 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 6575827 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 6575827 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 6575840 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 6575840 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.324027 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.324027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.324028 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.324028 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 26390.904406 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 26390.904406 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 26390.817706 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 26390.817706 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::.writebacks 1584755 # number of writebacks system.cpu.dcache.writebacks::total 1584755 # number of writebacks system.cpu.dcache.demand_mshr_hits::.cpu.data 5 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::.cpu.data 5 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses::.cpu.data 2130741 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2130741 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 2130748 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2130748 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 51970363000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 51970363000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 51971140000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 51971140000 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.324026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.324026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.324027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.324027 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 24390.746224 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 24390.746224 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 24391.030755 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 24391.030755 # average overall mshr miss latency system.cpu.dcache.replacements 2129725 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 2233893 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2233893 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 2120210 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2120210 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 55479201000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 55479201000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 4354103 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 4354103 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.486945 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.486945 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 26166.842435 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 26166.842435 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 5 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 2120205 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 2120205 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 51238322000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 51238322000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.486944 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.486944 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 24166.682939 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24166.682939 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 2211188 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 2211188 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 10528 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 10528 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 752681000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 752681000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 2221716 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 2221716 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.004739 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.004739 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 71493.256079 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 71493.256079 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 10528 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 10528 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 731625000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 731625000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.004739 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004739 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 69493.256079 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69493.256079 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_hits::.cpu.data 6 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 6 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_misses::.cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_accesses::.cpu.data 13 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 13 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.538462 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.538462 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 7 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 7 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 777000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 777000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.538462 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.538462 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 111000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 111000 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_misses::.cpu.data 8 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 8 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 432000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 432000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_accesses::.cpu.data 8 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 8 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 54000 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 54000 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 8 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 8 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 416000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 416000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 52000 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 52000 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 101 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 101 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 95000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 95000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 102 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 102 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.009804 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.009804 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 95000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 95000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 93000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 93000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.009804 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.009804 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 93000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 93000 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_hits::.cpu.data 102 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 102 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 102 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 102 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 1021.545685 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 6576039 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2130749 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 3.086257 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 236000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 1021.545685 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.997603 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997603 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 766 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 15282837 # Number of tag accesses system.cpu.dcache.tags.data_accesses 15282837 # Number of data accesses system.l2cache.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.l2cache.demand_hits::.cpu.inst 152 # number of demand (read+write) hits system.l2cache.demand_hits::.cpu.data 2119779 # number of demand (read+write) hits system.l2cache.demand_hits::total 2119931 # number of demand (read+write) hits system.l2cache.overall_hits::.cpu.inst 152 # number of overall hits system.l2cache.overall_hits::.cpu.data 2119779 # number of overall hits system.l2cache.overall_hits::total 2119931 # number of overall hits system.l2cache.demand_misses::.cpu.inst 919 # number of demand (read+write) misses system.l2cache.demand_misses::.cpu.data 10962 # number of demand (read+write) misses system.l2cache.demand_misses::total 11881 # number of demand (read+write) misses system.l2cache.overall_misses::.cpu.inst 919 # number of overall misses system.l2cache.overall_misses::.cpu.data 10962 # number of overall misses system.l2cache.overall_misses::total 11881 # number of overall misses system.l2cache.demand_miss_latency::.cpu.inst 90129000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::.cpu.data 1063234000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::total 1153363000 # number of demand (read+write) miss cycles system.l2cache.overall_miss_latency::.cpu.inst 90129000 # number of overall miss cycles system.l2cache.overall_miss_latency::.cpu.data 1063234000 # number of overall miss cycles system.l2cache.overall_miss_latency::total 1153363000 # number of overall miss cycles system.l2cache.demand_accesses::.cpu.inst 1071 # number of demand (read+write) accesses system.l2cache.demand_accesses::.cpu.data 2130741 # number of demand (read+write) accesses system.l2cache.demand_accesses::total 2131812 # number of demand (read+write) accesses system.l2cache.overall_accesses::.cpu.inst 1071 # number of overall (read+write) accesses system.l2cache.overall_accesses::.cpu.data 2130741 # number of overall (read+write) accesses system.l2cache.overall_accesses::total 2131812 # number of overall (read+write) accesses system.l2cache.demand_miss_rate::.cpu.inst 0.858077 # miss rate for demand accesses system.l2cache.demand_miss_rate::.cpu.data 0.005145 # miss rate for demand accesses system.l2cache.demand_miss_rate::total 0.005573 # miss rate for demand accesses system.l2cache.overall_miss_rate::.cpu.inst 0.858077 # miss rate for overall accesses system.l2cache.overall_miss_rate::.cpu.data 0.005145 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.005573 # miss rate for overall accesses system.l2cache.demand_avg_miss_latency::.cpu.inst 98072.905332 # average overall miss latency system.l2cache.demand_avg_miss_latency::.cpu.data 96992.702062 # average overall miss latency system.l2cache.demand_avg_miss_latency::total 97076.256207 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.inst 98072.905332 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.data 96992.702062 # average overall miss latency system.l2cache.overall_avg_miss_latency::total 97076.256207 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2cache.writebacks::.writebacks 5675 # number of writebacks system.l2cache.writebacks::total 5675 # number of writebacks system.l2cache.demand_mshr_misses::.cpu.inst 919 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::.cpu.data 10962 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::total 11881 # number of demand (read+write) MSHR misses system.l2cache.overall_mshr_misses::.cpu.inst 919 # number of overall MSHR misses system.l2cache.overall_mshr_misses::.cpu.data 10962 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 11881 # number of overall MSHR misses system.l2cache.demand_mshr_miss_latency::.cpu.inst 71749000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::.cpu.data 843994000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::total 915743000 # number of demand (read+write) MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.inst 71749000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.data 843994000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::total 915743000 # number of overall MSHR miss cycles system.l2cache.demand_mshr_miss_rate::.cpu.inst 0.858077 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::.cpu.data 0.005145 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::total 0.005573 # mshr miss rate for demand accesses system.l2cache.overall_mshr_miss_rate::.cpu.inst 0.858077 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::.cpu.data 0.005145 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.005573 # mshr miss rate for overall accesses system.l2cache.demand_avg_mshr_miss_latency::.cpu.inst 78072.905332 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::.cpu.data 76992.702062 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::total 77076.256207 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.inst 78072.905332 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.data 76992.702062 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 77076.256207 # average overall mshr miss latency system.l2cache.replacements 7794 # number of replacements system.l2cache.WritebackDirty_hits::.writebacks 1584755 # number of WritebackDirty hits system.l2cache.WritebackDirty_hits::total 1584755 # number of WritebackDirty hits system.l2cache.WritebackDirty_accesses::.writebacks 1584755 # number of WritebackDirty accesses(hits+misses) system.l2cache.WritebackDirty_accesses::total 1584755 # number of WritebackDirty accesses(hits+misses) system.l2cache.CleanEvict_mshr_misses::.writebacks 113 # number of CleanEvict MSHR misses system.l2cache.CleanEvict_mshr_misses::total 113 # number of CleanEvict MSHR misses system.l2cache.CleanEvict_mshr_miss_rate::.writebacks inf # mshr miss rate for CleanEvict accesses system.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2cache.ReadExReq_hits::.cpu.data 4116 # number of ReadExReq hits system.l2cache.ReadExReq_hits::total 4116 # number of ReadExReq hits system.l2cache.ReadExReq_misses::.cpu.data 6412 # number of ReadExReq misses system.l2cache.ReadExReq_misses::total 6412 # number of ReadExReq misses system.l2cache.ReadExReq_miss_latency::.cpu.data 613605000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_miss_latency::total 613605000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_accesses::.cpu.data 10528 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 10528 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_miss_rate::.cpu.data 0.609043 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_miss_rate::total 0.609043 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_miss_latency::.cpu.data 95696.350593 # average ReadExReq miss latency system.l2cache.ReadExReq_avg_miss_latency::total 95696.350593 # average ReadExReq miss latency system.l2cache.ReadExReq_mshr_misses::.cpu.data 6412 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 6412 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_miss_latency::.cpu.data 485365000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_latency::total 485365000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::.cpu.data 0.609043 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 0.609043 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_mshr_miss_latency::.cpu.data 75696.350593 # average ReadExReq mshr miss latency system.l2cache.ReadExReq_avg_mshr_miss_latency::total 75696.350593 # average ReadExReq mshr miss latency system.l2cache.ReadSharedReq_hits::.cpu.inst 152 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::.cpu.data 2115663 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 2115815 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_misses::.cpu.inst 919 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::.cpu.data 4550 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::total 5469 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_miss_latency::.cpu.inst 90129000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::.cpu.data 449629000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::total 539758000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_accesses::.cpu.inst 1071 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::.cpu.data 2120213 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::total 2121284 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_miss_rate::.cpu.inst 0.858077 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::.cpu.data 0.002146 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::total 0.002578 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.inst 98072.905332 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.data 98819.560440 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::total 98694.093984 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_mshr_misses::.cpu.inst 919 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::.cpu.data 4550 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::total 5469 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.inst 71749000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.data 358629000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::total 430378000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.inst 0.858077 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.data 0.002146 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.002578 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.inst 78072.905332 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 78819.560440 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78694.093984 # average ReadSharedReq mshr miss latency system.l2cache.InvalidateReq_misses::.cpu.data 8 # number of InvalidateReq misses system.l2cache.InvalidateReq_misses::total 8 # number of InvalidateReq misses system.l2cache.InvalidateReq_accesses::.cpu.data 8 # number of InvalidateReq accesses(hits+misses) system.l2cache.InvalidateReq_accesses::total 8 # number of InvalidateReq accesses(hits+misses) system.l2cache.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_mshr_misses::.cpu.data 8 # number of InvalidateReq MSHR misses system.l2cache.InvalidateReq_mshr_misses::total 8 # number of InvalidateReq MSHR misses system.l2cache.InvalidateReq_mshr_miss_latency::.cpu.data 232000 # number of InvalidateReq MSHR miss cycles system.l2cache.InvalidateReq_mshr_miss_latency::total 232000 # number of InvalidateReq MSHR miss cycles system.l2cache.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_avg_mshr_miss_latency::.cpu.data 29000 # average InvalidateReq mshr miss latency system.l2cache.InvalidateReq_avg_mshr_miss_latency::total 29000 # average InvalidateReq mshr miss latency system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.l2cache.tags.tagsinuse 4066.240096 # Cycle average of tags in use system.l2cache.tags.total_refs 4262238 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 11890 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 358.472498 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 86000 # Cycle when the warmup percentage was hit. system.l2cache.tags.occ_blocks::.writebacks 0.195068 # Average occupied blocks per requestor system.l2cache.tags.occ_blocks::.cpu.inst 17.911605 # Average occupied blocks per requestor system.l2cache.tags.occ_blocks::.cpu.data 4048.133423 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::.writebacks 0.000048 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::.cpu.inst 0.004373 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::.cpu.data 0.988314 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.992734 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::3 387 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::4 3508 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 34110762 # Number of tag accesses system.l2cache.tags.data_accesses 34110762 # Number of data accesses system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 97881415000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::.cpu.inst 58816 # Number of bytes read from this memory system.mem_ctrl.bytes_read::.cpu.data 701568 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 760384 # Number of bytes read from this memory system.mem_ctrl.bytes_inst_read::.cpu.inst 58816 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_inst_read::total 58816 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_written::.writebacks 363200 # Number of bytes written to this memory system.mem_ctrl.bytes_written::total 363200 # Number of bytes written to this memory system.mem_ctrl.num_reads::.cpu.inst 919 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::.cpu.data 10962 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 11881 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::.writebacks 5675 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 5675 # Number of write requests responded to by this memory system.mem_ctrl.bw_read::.cpu.inst 600890 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::.cpu.data 7167530 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::total 7768421 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::.cpu.inst 600890 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::total 600890 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_write::.writebacks 3710612 # Write bandwidth from this memory (bytes/s) system.mem_ctrl.bw_write::total 3710612 # Write bandwidth from this memory (bytes/s) system.mem_ctrl.bw_total::.writebacks 3710612 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.inst 600890 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.data 7167530 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::total 11479033 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.avgPriority_.writebacks::samples 5675.00 # Average QoS priority value for accepted requests system.mem_ctrl.avgPriority_.cpu.inst::samples 919.00 # Average QoS priority value for accepted requests system.mem_ctrl.avgPriority_.cpu.data::samples 10683.00 # Average QoS priority value for accepted requests system.mem_ctrl.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) system.mem_ctrl.priorityMaxLatency 0.004491694500 # per QoS priority maximum request to response latency (s) system.mem_ctrl.numReadWriteTurnArounds 316 # Number of turnarounds from READ to WRITE system.mem_ctrl.numWriteReadTurnArounds 316 # Number of turnarounds from WRITE to READ system.mem_ctrl.numStayReadState 53975 # Number of times bus staying in READ state system.mem_ctrl.numStayWriteState 5354 # Number of times bus staying in WRITE state system.mem_ctrl.readReqs 11881 # Number of read requests accepted system.mem_ctrl.writeReqs 5675 # Number of write requests accepted system.mem_ctrl.readBursts 11881 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 5675 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrl.servicedByWrQ 279 # Number of DRAM read bursts serviced by the write queue system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 822 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 792 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 727 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 639 # Per bank write bursts system.mem_ctrl.perBankRdBursts::4 576 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 590 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 679 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 711 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 700 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 736 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 745 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 801 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 807 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 826 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 722 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 729 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 333 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 298 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 300 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 292 # Per bank write bursts system.mem_ctrl.perBankWrBursts::4 308 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 290 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 363 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 418 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 432 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 417 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 431 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 408 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 406 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 387 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 284 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 283 # Per bank write bursts system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 23.84 # Average write queue length when enqueuing system.mem_ctrl.totQLat 91427000 # Total ticks spent queuing system.mem_ctrl.totBusLat 58010000 # Total ticks spent in databus transfers system.mem_ctrl.totMemAccLat 308964500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.avgQLat 7880.28 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrl.avgMemAccLat 26630.28 # Average memory access latency per DRAM burst system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrl.readRowHits 8603 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 4850 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 74.15 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate 85.46 # Row buffer hit rate for writes system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::6 11881 # Read request sizes (log2) system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 5675 # Write request sizes (log2) system.mem_ctrl.rdQLenPdf::0 11599 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 3 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 298 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 298 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::17 317 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::18 317 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 317 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 317 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 317 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::22 317 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 317 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 317 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 316 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::26 316 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::27 316 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::28 316 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::29 316 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 316 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 316 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::32 316 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 3798 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::mean 290.679305 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::gmean 152.504020 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::stdev 344.612741 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::0-127 2042 53.77% 53.77% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::128-255 516 13.59% 67.35% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::256-383 195 5.13% 72.49% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::384-511 147 3.87% 76.36% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::512-639 110 2.90% 79.25% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 116 3.05% 82.31% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 140 3.69% 85.99% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::896-1023 88 2.32% 88.31% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 444 11.69% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 3798 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 316 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::mean 36.645570 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::gmean 20.784193 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::stdev 250.660855 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::0-255 315 99.68% 99.68% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::4352-4607 1 0.32% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 316 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 316 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 17.879747 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 17.872976 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::stdev 0.476197 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 19 6.01% 6.01% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::18 297 93.99% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 316 # Writes before turning the bus around for reads system.mem_ctrl.bytesReadDRAM 742528 # Total number of bytes read from DRAM system.mem_ctrl.bytesReadWrQ 17856 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 361600 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 760384 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 363200 # Total written bytes from the system interface side system.mem_ctrl.avgRdBW 7.59 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 3.69 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 7.77 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 3.71 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 0.09 # Data bus utilization in percentage system.mem_ctrl.busUtilRead 0.06 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.mem_ctrl.totGap 97881320000 # Total gap between requests system.mem_ctrl.avgGap 5575377.08 # Average gap between requests system.mem_ctrl.masterReadBytes::.cpu.inst 58816 # Per-master bytes read from memory system.mem_ctrl.masterReadBytes::.cpu.data 683712 # Per-master bytes read from memory system.mem_ctrl.masterWriteBytes::.writebacks 361600 # Per-master bytes write to memory system.mem_ctrl.masterReadRate::.cpu.inst 600890.373315506265 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterReadRate::.cpu.data 6985105.395135532133 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterWriteRate::.writebacks 3694266.168914701324 # Per-master bytes write to memory rate (Bytes/sec) system.mem_ctrl.masterReadAccesses::.cpu.inst 919 # Per-master read serviced memory accesses system.mem_ctrl.masterReadAccesses::.cpu.data 10962 # Per-master read serviced memory accesses system.mem_ctrl.masterWriteAccesses::.writebacks 5675 # Per-master write serviced memory accesses system.mem_ctrl.masterReadTotalLat::.cpu.inst 24570750 # Per-master read total memory access latency system.mem_ctrl.masterReadTotalLat::.cpu.data 284393750 # Per-master read total memory access latency system.mem_ctrl.masterWriteTotalLat::.writebacks 2242910719250 # Per-master write total memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.inst 26736.40 # Per-master read average memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.data 25943.60 # Per-master read average memory access latency system.mem_ctrl.masterWriteAvgLat::.writebacks 395226558.46 # Per-master write average memory access latency system.mem_ctrl.pageHitRate 77.87 # Row buffer hit rate, read and write combined system.mem_ctrl.rank1.actEnergy 15001140 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank1.preEnergy 7973295 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank1.readEnergy 43311240 # Energy for read commands per rank (pJ) system.mem_ctrl.rank1.writeEnergy 15910560 # Energy for write commands per rank (pJ) system.mem_ctrl.rank1.refreshEnergy 7726639440.000001 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank1.actBackEnergy 4102652520 # Energy for active background per rank (pJ) system.mem_ctrl.rank1.preBackEnergy 34131598080 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank1.totalEnergy 46043086275 # Total energy per rank (pJ) system.mem_ctrl.rank1.averagePower 470.396615 # Core power per rank (mW) system.mem_ctrl.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank1.memoryStateTime::IDLE 88690180250 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::REF 3268460000 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::ACT 5922774750 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl.rank0.actEnergy 12123720 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank0.preEnergy 6440115 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank0.readEnergy 39527040 # Energy for read commands per rank (pJ) system.mem_ctrl.rank0.writeEnergy 13582440 # Energy for write commands per rank (pJ) system.mem_ctrl.rank0.refreshEnergy 7726639440.000001 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank0.actBackEnergy 3374867970 # Energy for active background per rank (pJ) system.mem_ctrl.rank0.preBackEnergy 34744469280 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank0.totalEnergy 45917650005 # Total energy per rank (pJ) system.mem_ctrl.rank0.averagePower 469.115102 # Core power per rank (mW) system.mem_ctrl.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank0.memoryStateTime::IDLE 90291690000 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::REF 3268460000 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT 4321265000 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states ---------- End Simulation Statistics ----------