---------- Begin Simulation Statistics ---------- final_tick 51337000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 476104 # Simulator instruction rate (inst/s) host_mem_usage 796252 # Number of bytes of host memory used host_op_rate 539678 # Simulator op (including micro ops) rate (op/s) host_seconds 0.01 # Real time elapsed on the host host_tick_rate 4313280783 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5606 # Number of instructions simulated sim_ops 6415 # Number of ops (including micro ops) simulated sim_seconds 0.000051 # Number of seconds simulated sim_ticks 51337000 # Number of ticks simulated system.cpu.Branches 1250 # Number of branches fetched system.cpu.committedInsts 5606 # Number of instructions committed system.cpu.committedOps 6415 # Number of ops (including micro ops) committed system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.numCycles 51337 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 51336.999000 # Number of busy cycles system.cpu.num_cc_register_reads 22880 # number of times the CC registers were read system.cpu.num_cc_register_writes 2955 # number of times the CC registers were written system.cpu.num_conditional_control_insts 910 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_func_calls 233 # number of times a function call or return occured system.cpu.num_idle_cycles 0.001000 # Number of idle cycles system.cpu.num_int_alu_accesses 5510 # Number of integer alu accesses system.cpu.num_int_insts 5510 # number of integer instructions system.cpu.num_int_register_reads 8739 # number of times the integer registers were read system.cpu.num_int_register_writes 3406 # number of times the integer registers were written system.cpu.num_load_insts 1173 # Number of load instructions system.cpu.num_mem_refs 2141 # number of memory refs system.cpu.num_store_insts 968 # Number of store instructions system.cpu.num_vec_alu_accesses 0 # Number of vector alu accesses system.cpu.num_vec_insts 0 # number of vector instructions system.cpu.num_vec_register_reads 16 # number of times the vector registers were read system.cpu.num_vec_register_writes 0 # number of times the vector registers were written system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 4328 66.83% 66.83% # Class of executed instruction system.cpu.op_class::IntMult 4 0.06% 66.89% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::FloatMultAcc 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::FloatMisc 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdAlu 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdCmp 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdCvt 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdMisc 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdMult 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdMultAcc 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdShift 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdShiftAcc 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdDiv 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdSqrt 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdFloatAdd 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdFloatAlu 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 66.89% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 3 0.05% 66.94% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdReduceAdd 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdReduceAlu 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdReduceCmp 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdFloatReduceAdd 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdFloatReduceCmp 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdAes 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdAesMix 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdSha1Hash 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdSha1Hash2 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdSha256Hash 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdSha256Hash2 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdShaSigma2 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdShaSigma3 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::SimdPredAlu 0 0.00% 66.94% # Class of executed instruction system.cpu.op_class::MemRead 1173 18.11% 85.05% # Class of executed instruction system.cpu.op_class::MemWrite 968 14.95% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6476 # Class of executed instruction system.cpu.workload.numSyscalls 13 # Number of system calls system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 351 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 351 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 351 # Request fanout histogram system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) system.membus.respLayer0.occupancy 1866750 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.6 # Layer utilization (%) system.l2bus.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 348 # Transaction distribution system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) system.l2bus.snoop_fanout::samples 391 # Request fanout histogram system.l2bus.snoop_fanout::mean 0.086957 # Request fanout histogram system.l2bus.snoop_fanout::stdev 0.282132 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.l2bus.snoop_fanout::0 357 91.30% 91.30% # Request fanout histogram system.l2bus.snoop_fanout::1 34 8.70% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 391 # Request fanout histogram system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.cpu.numPwrStateTransitions 1 # Number of power state transitions system.cpu.pwrStateResidencyTicks::ON 51337000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 5396 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 5396 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 5396 # number of overall hits system.cpu.icache.overall_hits::total 5396 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 249 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 23685000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 23685000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 23685000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 23685000 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 5645 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 5645 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 5645 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5645 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.044110 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.044110 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.044110 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.044110 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 95120.481928 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 95120.481928 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 95120.481928 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 95120.481928 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.demand_mshr_misses::.cpu.inst 249 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 249 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 23187000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 23187000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 23187000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 23187000 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.044110 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.044110 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.044110 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.044110 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 93120.481928 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 93120.481928 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 93120.481928 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 93120.481928 # average overall mshr miss latency system.cpu.icache.replacements 70 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 5396 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5396 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 249 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 23685000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 23685000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 5645 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5645 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.044110 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.044110 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 95120.481928 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 95120.481928 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 249 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 23187000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 23187000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.044110 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.044110 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 93120.481928 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93120.481928 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 96.896782 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5645 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22.670683 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 107000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 96.896782 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.378503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.378503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11539 # Number of tag accesses system.cpu.icache.tags.data_accesses 11539 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 1932 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 1932 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 1932 # number of overall hits system.cpu.dcache.overall_hits::total 1932 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 142 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 142 # number of overall misses system.cpu.dcache.overall_misses::total 142 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 12955000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 12955000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 12955000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 12955000 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 2074 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 2074 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 2074 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2074 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.068467 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.068467 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.068467 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.068467 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 91232.394366 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 91232.394366 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 91232.394366 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 91232.394366 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.demand_mshr_misses::.cpu.data 142 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 12671000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 12671000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 12671000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12671000 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.068467 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.068467 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.068467 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.068467 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 89232.394366 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 89232.394366 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 89232.394366 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 89232.394366 # average overall mshr miss latency system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 1032 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1032 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 99 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 8567000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 8567000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 1131 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1131 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.087533 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.087533 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 86535.353535 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 86535.353535 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 99 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 8369000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 8369000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.087533 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.087533 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 84535.353535 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84535.353535 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 900 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 900 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 43 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 4388000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 943 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 943 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.045599 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.045599 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 102046.511628 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 43 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 4302000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.045599 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045599 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 100046.511628 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits::.cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 84.704736 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2096 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14.760563 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 135000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 84.704736 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.082719 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.082719 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses system.l2cache.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.l2cache.demand_hits::.cpu.inst 24 # number of demand (read+write) hits system.l2cache.demand_hits::.cpu.data 16 # number of demand (read+write) hits system.l2cache.demand_hits::total 40 # number of demand (read+write) hits system.l2cache.overall_hits::.cpu.inst 24 # number of overall hits system.l2cache.overall_hits::.cpu.data 16 # number of overall hits system.l2cache.overall_hits::total 40 # number of overall hits system.l2cache.demand_misses::.cpu.inst 225 # number of demand (read+write) misses system.l2cache.demand_misses::.cpu.data 126 # number of demand (read+write) misses system.l2cache.demand_misses::total 351 # number of demand (read+write) misses system.l2cache.overall_misses::.cpu.inst 225 # number of overall misses system.l2cache.overall_misses::.cpu.data 126 # number of overall misses system.l2cache.overall_misses::total 351 # number of overall misses system.l2cache.demand_miss_latency::.cpu.inst 21896000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::.cpu.data 11881000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::total 33777000 # number of demand (read+write) miss cycles system.l2cache.overall_miss_latency::.cpu.inst 21896000 # number of overall miss cycles system.l2cache.overall_miss_latency::.cpu.data 11881000 # number of overall miss cycles system.l2cache.overall_miss_latency::total 33777000 # number of overall miss cycles system.l2cache.demand_accesses::.cpu.inst 249 # number of demand (read+write) accesses system.l2cache.demand_accesses::.cpu.data 142 # number of demand (read+write) accesses system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses system.l2cache.overall_accesses::.cpu.inst 249 # number of overall (read+write) accesses system.l2cache.overall_accesses::.cpu.data 142 # number of overall (read+write) accesses system.l2cache.overall_accesses::total 391 # number of overall (read+write) accesses system.l2cache.demand_miss_rate::.cpu.inst 0.903614 # miss rate for demand accesses system.l2cache.demand_miss_rate::.cpu.data 0.887324 # miss rate for demand accesses system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses system.l2cache.overall_miss_rate::.cpu.inst 0.903614 # miss rate for overall accesses system.l2cache.overall_miss_rate::.cpu.data 0.887324 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses system.l2cache.demand_avg_miss_latency::.cpu.inst 97315.555556 # average overall miss latency system.l2cache.demand_avg_miss_latency::.cpu.data 94293.650794 # average overall miss latency system.l2cache.demand_avg_miss_latency::total 96230.769231 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.inst 97315.555556 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.data 94293.650794 # average overall miss latency system.l2cache.overall_avg_miss_latency::total 96230.769231 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2cache.demand_mshr_misses::.cpu.inst 225 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::.cpu.data 126 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.l2cache.overall_mshr_misses::.cpu.inst 225 # number of overall MSHR misses system.l2cache.overall_mshr_misses::.cpu.data 126 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses system.l2cache.demand_mshr_miss_latency::.cpu.inst 17396000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::.cpu.data 9361000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::total 26757000 # number of demand (read+write) MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.inst 17396000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.data 9361000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::total 26757000 # number of overall MSHR miss cycles system.l2cache.demand_mshr_miss_rate::.cpu.inst 0.903614 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::.cpu.data 0.887324 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses system.l2cache.overall_mshr_miss_rate::.cpu.inst 0.903614 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::.cpu.data 0.887324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses system.l2cache.demand_avg_mshr_miss_latency::.cpu.inst 77315.555556 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::.cpu.data 74293.650794 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::total 76230.769231 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.inst 77315.555556 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.data 74293.650794 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 76230.769231 # average overall mshr miss latency system.l2cache.replacements 0 # number of replacements system.l2cache.ReadExReq_misses::.cpu.data 43 # number of ReadExReq misses system.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses system.l2cache.ReadExReq_miss_latency::.cpu.data 4173000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_accesses::.cpu.data 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_miss_rate::.cpu.data 1 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_miss_latency::.cpu.data 97046.511628 # average ReadExReq miss latency system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency system.l2cache.ReadExReq_mshr_misses::.cpu.data 43 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_miss_latency::.cpu.data 3313000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_mshr_miss_latency::.cpu.data 77046.511628 # average ReadExReq mshr miss latency system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency system.l2cache.ReadSharedReq_hits::.cpu.inst 24 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::.cpu.data 16 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_misses::.cpu.inst 225 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::.cpu.data 83 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_miss_latency::.cpu.inst 21896000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::.cpu.data 7708000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::total 29604000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_accesses::.cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::.cpu.data 99 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_miss_rate::.cpu.inst 0.903614 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::.cpu.data 0.838384 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.inst 97315.555556 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.data 92867.469880 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::total 96116.883117 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_mshr_misses::.cpu.inst 225 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::.cpu.data 83 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.inst 17396000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.data 6048000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::total 23444000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.inst 77315.555556 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 72867.469880 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76116.883117 # average ReadSharedReq mshr miss latency system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.l2cache.tags.tagsinuse 185.008029 # Cycle average of tags in use system.l2cache.tags.total_refs 451 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 1.284900 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 86000 # Cycle when the warmup percentage was hit. system.l2cache.tags.occ_blocks::.cpu.inst 107.654228 # Average occupied blocks per requestor system.l2cache.tags.occ_blocks::.cpu.data 77.353800 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::.cpu.inst 0.026283 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::.cpu.data 0.018885 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.045168 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3959 # Number of tag accesses system.l2cache.tags.data_accesses 3959 # Number of data accesses system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 51337000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::.cpu.inst 14400 # Number of bytes read from this memory system.mem_ctrl.bytes_read::.cpu.data 8064 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory system.mem_ctrl.bytes_inst_read::.cpu.inst 14400 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory system.mem_ctrl.num_reads::.cpu.inst 225 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::.cpu.data 126 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory system.mem_ctrl.bw_read::.cpu.inst 280499445 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::.cpu.data 157079689 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::total 437579134 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::.cpu.inst 280499445 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::total 280499445 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.inst 280499445 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.data 157079689 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::total 437579134 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.avgPriority_.cpu.inst::samples 225.00 # Average QoS priority value for accepted requests system.mem_ctrl.avgPriority_.cpu.data::samples 126.00 # Average QoS priority value for accepted requests system.mem_ctrl.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) system.mem_ctrl.priorityMaxLatency 0.000000495000 # per QoS priority maximum request to response latency (s) system.mem_ctrl.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE system.mem_ctrl.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ system.mem_ctrl.numStayReadState 714 # Number of times bus staying in READ state system.mem_ctrl.numStayWriteState 0 # Number of times bus staying in WRITE state system.mem_ctrl.readReqs 351 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing system.mem_ctrl.totQLat 2163000 # Total ticks spent queuing system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers system.mem_ctrl.totMemAccLat 8744250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.avgQLat 6162.39 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrl.avgMemAccLat 24912.39 # Average memory access latency per DRAM burst system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrl.readRowHits 271 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 77.21 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::mean 288.426667 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::gmean 196.710491 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::stdev 275.851565 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::0-127 18 24.00% 24.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::128-255 26 34.67% 58.67% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::256-383 12 16.00% 74.67% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 80.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::512-639 7 9.33% 89.33% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side system.mem_ctrl.avgRdBW 437.58 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 437.58 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 3.42 # Data bus utilization in percentage system.mem_ctrl.busUtilRead 3.42 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.totGap 51238000 # Total gap between requests system.mem_ctrl.avgGap 145977.21 # Average gap between requests system.mem_ctrl.masterReadBytes::.cpu.inst 14400 # Per-master bytes read from memory system.mem_ctrl.masterReadBytes::.cpu.data 8064 # Per-master bytes read from memory system.mem_ctrl.masterReadRate::.cpu.inst 280499444.844848752022 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterReadRate::.cpu.data 157079689.113115310669 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterReadAccesses::.cpu.inst 225 # Per-master read serviced memory accesses system.mem_ctrl.masterReadAccesses::.cpu.data 126 # Per-master read serviced memory accesses system.mem_ctrl.masterReadTotalLat::.cpu.inst 5847000 # Per-master read total memory access latency system.mem_ctrl.masterReadTotalLat::.cpu.data 2897250 # Per-master read total memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.inst 25986.67 # Per-master read average memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.data 22994.05 # Per-master read average memory access latency system.mem_ctrl.pageHitRate 77.21 # Row buffer hit rate, read and write combined system.mem_ctrl.rank1.actEnergy 185640 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank1.preEnergy 91080 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank1.readEnergy 692580 # Energy for read commands per rank (pJ) system.mem_ctrl.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl.rank1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank1.actBackEnergy 20736600 # Energy for active background per rank (pJ) system.mem_ctrl.rank1.preBackEnergy 2251200 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank1.totalEnergy 27644940 # Total energy per rank (pJ) system.mem_ctrl.rank1.averagePower 538.499328 # Core power per rank (mW) system.mem_ctrl.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank1.memoryStateTime::IDLE 5681500 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::ACT 44095500 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl.rank0.actEnergy 385560 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank0.preEnergy 193545 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank0.readEnergy 1813560 # Energy for read commands per rank (pJ) system.mem_ctrl.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl.rank0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank0.actBackEnergy 22159320 # Energy for active background per rank (pJ) system.mem_ctrl.rank0.preBackEnergy 1053120 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank0.totalEnergy 29292945 # Total energy per rank (pJ) system.mem_ctrl.rank0.averagePower 570.601028 # Core power per rank (mW) system.mem_ctrl.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank0.memoryStateTime::IDLE 2546750 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT 47230250 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states ---------- End Simulation Statistics ----------