1.
a) According to the homepage, GEM5 supports the following ISAs:
Alpha, ARM, SPARC, MIPS, POWER, RISC-V and x86 ISAs.

b) DONE

c) CPU models are found here: https://www.gem5.org/documentation/general_docs/cpu_models/SimpleCPU 

The CPU model in the tutorial was the "TimingSimpleCPU", the most simple timing-based model. It executes each instr in a single Tc, except mem requests which flow through the mem system.
It is derived from the 'SimpleCPU' model, which also includes 'AtomicSimpleCPU'.

	*AtomicSimpleCPU: uses atomic memory accesses. It uses the latency estimates from the atomic accesses to estimate overall cache access time. 
	*TimingSimpleCPU: uses timing memory accesses. It stalls on cache accesses and waits for the memory system to respond prior to proceeding. 

	*O3CPU: OoO model
	*TraceCPU:
	'MinorCPU: in-order CPU.
	*DerivO3CPU: out-of-order CPU.
	
d)