=================================================================== = Peer Review = = = = "A design approach for Sorting Networks and their Applications" = = Maria Aguilar R. = = Namratha Sanjay = =================================================================== I've left comments directly in the PDF, and will lay out a few (more general) ones here. I've tried to be as constructive as possible, so I hope this helps. I've tried to ignore language-based criticism as much as possible, but sometimes things simply aren't understandable. You need to take greater care with the language, and I mean this only constructively, but maybe get someone outside the group to read it before sending it in next time. I can not review what I don't understand. :) Summary: it looks promising but needs to be significantly rewritten. Use your sources! Explain things in more detail! Best of luck in the rest of the course! -John ============ = COMMENTS = ============ INTRO: ====== * The third paragraph is clearly lifted straight from Wikipedia. I wasn't specifically looking for this, but saw it pretty immediately on the article for sorting networks... This is obviously not good (I believe the final version will have to pass Urkund https://www.urkund.com/), but it also does not really flow with the rest of the text, it introduces concepts without adequately explaining them. (three-state devices? What is a sorting "network"? Is it different from a switching network? Is it an algorithm or an implementation? Bitonic mergesort? Why is GPGPU mentioned here ? etc...). * The computational requirements are not really laid out, nor the need for more performance (beyond the obvious desire for faster execution!). Much later in the text it is mentioned that database management tools will benifit. MAIN TEXT: ========== * There is no roofline analysis. * The most computationally expensive components are not really identified, though the algorithmic time-complexity is. * You have started looking at different approaches to the scenario. CPU, GPU and FPGA, though the FPGA solution is not really compared to the others numerically. * The hardware components are somewhat discussed; the software less so. There is a large focus on achieving parallellism and why that is important, which is good. * Various trade-offs of the various hardware platforms are discussed in light detail but often lack explanation/sources. * Some state-of-the art methods are mentioned (bandwidth independent sorting, for instance), but not really examined. GENERAL: ======== * The presentation is very nice, though I believe they specifically asked for the ACM TACO template (http://www.acm.org/publications/authors/submissions). This is easy to implement; just use \documentclass[acmsmall]{acmart}. I'd also recommend starting from the ACM template that you can find on overleaf as it shows many additional parameters that can be used in the template. * Your paragraphing is inconsistent. At times you skip a line but mostly there is nothing to indicate a new paragraph. This may be an artefact of the IEEE style, but it makes it a little hard to read. * There are sometimes inappropriate usages of hence, nevertheless, thus etc... Be mindful of this and what the actual meaning is, as it can become quite confusing. * Many things are mentioned without context or not explained or simply (seemingly) irrelevant. (See the PDF).