INSTR cache il1 =============== stringsearch ------------ Hit latency: 1, assoc: 1, cache_size: 4096 sim_CPI 18.2057 # cycles per instruction Hit latency: 1, assoc: 1, cache_size: 8192 sim_CPI 12.7116 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 16384 sim_CPI 8.3466 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 32768 sim_CPI 3.6848 # cycles per instruction --------------------------------------------------------------- Hit latency: 1, assoc: 2, cache_size: 4096 sim_CPI 17.4704 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 8192 sim_CPI 10.5235 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 16384 sim_CPI 4.6121 # cycles per instruction Hit latency: 3, assoc: 2, cache_size: 32768 sim_CPI 3.2481 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 4, cache_size: 4096 sim_CPI 17.2740 # cycles per instruction Hit latency: 2, assoc: 4, cache_size: 8192 sim_CPI 9.8711 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 16384 sim_CPI 3.6674 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 32768 sim_CPI 2.7094 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 8, cache_size: 4096 sim_CPI 17.2158 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 8192 sim_CPI 9.0633 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 16384 sim_CPI 2.9832 # cycles per instruction Hit latency: 4, assoc: 8, cache_size: 32768 sim_CPI 2.7094 # cycles per instruction --------------------------------------------------------------- jpeg ------------ Hit latency: 1, assoc: 1, cache_size: 4096 sim_CPI 7.7762 # cycles per instruction Hit latency: 1, assoc: 1, cache_size: 8192 sim_CPI 6.5354 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 16384 sim_CPI 3.9476 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 32768 sim_CPI 3.7483 # cycles per instruction --------------------------------------------------------------- Hit latency: 1, assoc: 2, cache_size: 4096 sim_CPI 5.8863 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 8192 sim_CPI 3.7051 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 16384 sim_CPI 3.5988 # cycles per instruction Hit latency: 3, assoc: 2, cache_size: 32768 sim_CPI 3.5606 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 4, cache_size: 4096 sim_CPI 4.6820 # cycles per instruction Hit latency: 2, assoc: 4, cache_size: 8192 sim_CPI 3.6618 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 16384 sim_CPI 3.5703 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 32768 sim_CPI 3.5467 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 8, cache_size: 4096 sim_CPI 4.1375 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 8192 sim_CPI 3.6322 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 16384 sim_CPI 3.5680 # cycles per instruction Hit latency: 4, assoc: 8, cache_size: 32768 sim_CPI 3.5456 # cycles per instruction --------------------------------------------------------------- gsm ------------ Hit latency: 1, assoc: 1, cache_size: 4096 sim_CPI 3.5318 # cycles per instruction Hit latency: 1, assoc: 1, cache_size: 8192 sim_CPI 3.1024 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 16384 sim_CPI 2.8517 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 32768 sim_CPI 2.3070 # cycles per instruction --------------------------------------------------------------- Hit latency: 1, assoc: 2, cache_size: 4096 sim_CPI 3.3478 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 8192 sim_CPI 2.9491 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 16384 sim_CPI 2.5537 # cycles per instruction Hit latency: 3, assoc: 2, cache_size: 32768 sim_CPI 2.1130 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 4, cache_size: 4096 sim_CPI 3.0752 # cycles per instruction Hit latency: 2, assoc: 4, cache_size: 8192 sim_CPI 2.9859 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 16384 sim_CPI 2.4094 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 32768 sim_CPI 2.0082 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 8, cache_size: 4096 sim_CPI 3.0569 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 8192 sim_CPI 2.9945 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 16384 sim_CPI 2.4847 # cycles per instruction Hit latency: 4, assoc: 8, cache_size: 32768 sim_CPI 2.0078 # cycles per instruction --------------------------------------------------------------- qsort ------------ Hit latency: 1, assoc: 1, cache_size: 4096 sim_CPI 21.6554 # cycles per instruction Hit latency: 1, assoc: 1, cache_size: 8192 sim_CPI 11.7285 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 16384 sim_CPI 6.4776 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 32768 sim_CPI 6.0046 # cycles per instruction --------------------------------------------------------------- Hit latency: 1, assoc: 2, cache_size: 4096 sim_CPI 14.9852 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 8192 sim_CPI 11.7386 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 16384 sim_CPI 6.3335 # cycles per instruction Hit latency: 3, assoc: 2, cache_size: 32768 sim_CPI 5.8144 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 4, cache_size: 4096 sim_CPI 9.4803 # cycles per instruction Hit latency: 2, assoc: 4, cache_size: 8192 sim_CPI 5.9999 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 16384 sim_CPI 5.8148 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 32768 sim_CPI 5.8142 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 8, cache_size: 4096 sim_CPI 9.4523 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 8192 sim_CPI 5.8157 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 16384 sim_CPI 5.8147 # cycles per instruction Hit latency: 4, assoc: 8, cache_size: 32768 sim_CPI 5.8142 # cycles per instruction --------------------------------------------------------------- dijkstra ------------ Hit latency: 1, assoc: 1, cache_size: 4096 sim_CPI 8.1089 # cycles per instruction Hit latency: 1, assoc: 1, cache_size: 8192 sim_CPI 6.3645 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 16384 sim_CPI 4.5091 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 32768 sim_CPI 4.4450 # cycles per instruction --------------------------------------------------------------- Hit latency: 1, assoc: 2, cache_size: 4096 sim_CPI 8.7625 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 8192 sim_CPI 5.7115 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 16384 sim_CPI 4.3956 # cycles per instruction Hit latency: 3, assoc: 2, cache_size: 32768 sim_CPI 4.0100 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 4, cache_size: 4096 sim_CPI 8.8367 # cycles per instruction Hit latency: 2, assoc: 4, cache_size: 8192 sim_CPI 4.4745 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 16384 sim_CPI 4.0282 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 32768 sim_CPI 4.0006 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 8, cache_size: 4096 sim_CPI 9.8432 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 8192 sim_CPI 4.1220 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 16384 sim_CPI 4.0116 # cycles per instruction Hit latency: 4, assoc: 8, cache_size: 32768 sim_CPI 3.9988 # cycles per instruction ---------------------------------------------------------------