
################################################## Simulator program Configuration
# load configuration from a file
# -config               

# dump configuration to a file
# -dumpconfig           

# print help message
# -h                          false 

# verbose operation
# -v                          false 

# enable debug message
# -d                          false 

# start in Dlite debugger
# -i                          false 

# random number generator seed (0 for timer seed)
-seed                             1 

# initialize and terminate immediately
# -q                           true 

# restore EIO trace execution from <fname>
# -chkpt                     <null> 

# redirect simulator output to file (non-interactive only)
# -redir:sim                 <null> 

# redirect simulated program output to file
# -redir:prog                <null> 

# simulator scheduling priority
-nice                             0 

# run simulation with cost enable
-cost:enable                  false 

# maximum number of inst's to execute
-max:inst                         0 

# number of insts skipped before timing starts
-fastfwd                          0 

# generate pipetrace, i.e., <fname|stdout|stderr> <range>
# -ptrace                    <null> 

################################################## Core Configuration
# instruction fetch queue size (in insts)
-fetch:ifqsize                    4 

# extra branch mis-prediction latency
-fetch:mplat                      3 

# speed of front-end of machine relative to execution core
-fetch:speed                      1 

# branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}
-bpred                         comb

# bimodal predictor config (<table size>)
-bpred:bimod           1024 

# 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
-bpred:2lev            1 1024 8 0 

# combining predictor config (<meta_table_size>)
-bpred:comb            1024 

# return address stack size (0 for no return stack)
-bpred:ras                        1024 

# BTB config (<num_sets> <associativity>)
-bpred:btb             8 8 

# speculative predictors update in {ID|WB} (default non-spec)
# -bpred:spec_update         <null> 

# instruction decode B/W (insts/cycle)
-decode:width                     1 

# instruction issue B/W (insts/cycle)
-issue:width                      1 

# run pipeline with in-order issue
-issue:inorder                true 

# issue instructions down wrong execution paths
-issue:wrongpath               false 

# instruction commit B/W (insts/cycle)
-commit:width                     1 

# register update unit (RUU) size
-ruu:size                        16

# load/store queue (LSQ) size
-lsq:size                         8


################################################## Cache Configuration
# #########################
# The cache configuration (<config>) is formatted as follows: 
# <name>:<nsets>:<bsize>:<assoc>:<repl>
# Each of these fields has the following meaning:
# <name> cache name, must be unique.
# <nsets> number of sets in the cache.
# <bsize> block size (for TLBs, use the page size).
# <assoc> associativity of the cache (power of two). 
# <repl>replacement policy (l | f | r), wherel = LRU,f = FIFO,r = random replacement.
# The cache size is therefore the product of <nsets>, <bsize>, and<assoc>.

# l1 data cache config, i.e., {<config>|none}
-cache:dl1             dl1:128:128:2:l 

# l1 data cache hit latency (in cycles)
-cache:dl1lat                     3 

# l2 data cache config, i.e., {<config>|none}
-cache:dl2             none 

# l2 data cache hit latency (in cycles)
-cache:dl2lat                     4 

# l1 instruction cache config, i.e., {<config>|dl1|dl2|none}
-cache:il1             il1:64:128:4:l 

# l1 instruction cache hit latency (in cycles)
-cache:il1lat                     4 

# l2 instruction cache config, i.e., {<config>|dl2|none}
-cache:il2                    none  

# l2 instruction cache hit latency (in cycles)
-cache:il2lat                     4 

# flush caches on system calls
-cache:flush                  false 

# convert 64-bit inst addresses to 32-bit inst equivalents
-cache:icompress              false 

################################################## Memory Configuration
# memory access latency (<first_chunk> <inter_chunk>)
-mem:lat               200 0 

# memory access bus width (in bytes)
-mem:width                        8 

################################################## TLB Configuration
# instruction TLB config, i.e., {<config>|none}
-tlb:itlb              itlb:32:4096:4:l 

# data TLB config, i.e., {<config>|none}
-tlb:dtlb              dtlb:32:4096:4:l 

# inst/data TLB miss latency (in cycles)
-tlb:lat                         30 

################################################## Core Functional Units Configuration
# total number of integer ALU's available
-res:ialu                         1 

# total number of integer multiplier/dividers available
-res:imult                        1 

# total number of memory system ports available (to CPU)
-res:memport                      1 

# total number of floating point ALU's available
-res:fpalu                        1 

# total number of floating point multiplier/dividers available
-res:fpmult                       1 

################################################## Misc Configuration
# profile stat(s) against text addr's (mult uses ok)
# -pcstat                    <null> 

# operate in backward-compatible bugs mode (for testing only)
-bugcompat                    false 

