# Config file for Intel Silvermont-like architecture

[general]
enable_icache_modeling = true

[perf_model/core]
frequency = 2.4
logical_cpus = 1 # number of SMT threads per core
type = interval
core_model = nehalem

[perf_model/core/interval_timer]
dispatch_width = 2
window_size = 32
num_outstanding_loadstores = 10

[perf_model/sync]
reschedule_cost = 1000

[caching_protocol]
type = parametric_dram_directory_msi

[perf_model/branch_predictor]
type = pentium_m
mispredict_penalty=8 # Reflects just the front-end portion (approx) of the penalty for Interval Simulation

[perf_model/tlb]
penalty = 30          # Page walk penalty in cycles

[perf_model/itlb]
size = 48             # Number of I-TLB entries
associativity = 48    # I-TLB associativity

[perf_model/dtlb]
size = 48             # Number of D-TLB entries
associativity = 48    # D-TLB associativity

[perf_model/stlb]
size = 128            # Number of second-level TLB entries
associativity = 4     # S-TLB associativity

[perf_model/cache]
levels = 2

[perf_model/l1_icache]
perfect = false
cache_size = 32
associativity = 8
address_hash = mask
replacement_policy = lru
data_access_time = 4
tags_access_time = 1
perf_model_type = parallel
writethrough = 0
shared_cores = 1

[perf_model/l1_dcache]
perfect = false
cache_size = 24
associativity = 6
address_hash = mask
replacement_policy = lru
data_access_time = 4
tags_access_time = 1
perf_model_type = parallel
writethrough = 0
shared_cores = 1

[perf_model/l2_cache]
perfect = false
cache_size = 1024
associativity = 16
address_hash = mask
replacement_policy = lru
data_access_time = 12 # 13 or 14 cycles (including L1 tag miss) http://www.realworldtech.com/silvermont/7/
tags_access_time = 3
writeback_time = 50
perf_model_type = parallel
writethrough = 0
shared_cores = 2
dvfs_domain = global # L1 and L2 run at core frequency (default), L3 is system frequency
prefetcher = none

[perf_model/dram_directory]
# total_entries = number of entries per directory controller.
total_entries = 1048576
associativity = 16
directory_type = full_map

[perf_model/dram]
num_controllers = -1
controllers_interleaving = 4 # Two DDR3 controllers for a C2000 8-core Centerton, one for smaller chips
# DRAM access latency in nanoseconds. Should not include L1-LLC tag access time, directory access time (14 cycles = 5.2 ns),
# or network time [(cache line size + 2*{overhead=40}) / network bandwidth = 18 ns]
# Membench says 175 cycles @ 2.66 GHz = 66 ns total
latency = 45
per_controller_bandwidth = 12.8              # In GB/s
chips_per_dimm = 8
dimms_per_controller = 4

[network]
memory_model_1 = bus
memory_model_2 = bus

# In-die Interface (IDI)
[network/bus]
bandwidth = 128 # In GB/s
ignore_local_traffic = false

[clock_skew_minimization]
scheme = barrier

[clock_skew_minimization/barrier]
quantum = 100

[dvfs]
transition_latency = 2000 # In ns, "under 2 microseconds" according to http://download.intel.com/design/intarch/papers/323671.pdf (page 8)

[dvfs/simple]
cores_per_socket = 1

[power]
vdd = 1.0 # Volts
technology_node = 22 # nm
