Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version1957588
date_generatedFri Feb 16 10:48:36 2018 os_platformWIN64
product_versionVivado v2017.2.1 (64-bit) project_idbde1f87e133f4616bb0782373214a6e1
project_iteration1 random_id2a78ae3865a1502cb95fe264e371fba9
registration_id2a78ae3865a1502cb95fe264e371fba9 route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagecsg324 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-3470S CPU @ 2.90GHz cpu_speed2893 MHz
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
system_ram17.000 GB total_processors1

vivado_usage
java_command_handlers
addsrc=2 closeproject=0 editproperties=1 fileexit=3
launchimpact=1 newproject=1 projectsettings=1 runbitgen=4
runimplementation=2 runsynthesis=1 savefileproxyhandler=8 updatesourcefiles=1
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=2 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 carry4=24 fdce=104 fdpe=1
gnd=3 ibuf=5 lut1=38 lut2=10
lut3=51 lut4=5 lut5=6 obuf=32
vcc=3
pre_unisim_transformation
bufg=1 carry4=24 fdce=104 fdpe=1
gnd=3 ibuf=5 lut1=38 lut2=10
lut3=51 lut4=5 lut5=6 obuf=32
vcc=3

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
timing-18=36

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") clocks=0.000927 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.097093
die=xc7a100tcsg324-1 dsp_output_toggle=12.500000 dynamic=0.009680 effective_thetaja=4.6
enable_probability=0.990000 family=artix7 ff_toggle=12.500000 flow_state=routed
heatsink=medium (Medium Profile) i/o=0.008262 input_toggle=12.500000 junction_temp=25.5 (C)
logic=0.000241 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.106773
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=csg324
pct_clock_constrained=1.000000 pct_inputs_defined=20 platform=nt64 process=typical
ram_enable=50.000000 ram_write=50.000000 read_saif=False set/reset_probability=0.000000
signal_rate=False signals=0.000250 simulation_file=None speedgrade=-1
static_prob=False temp_grade=commercial thetajb=5.7 (C/W) thetasa=4.6 (C/W)
toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=4.6 user_junc_temp=25.5 (C)
user_thetajb=5.7 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000
vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000300 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.018141
vccaux_total_current=0.018441 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000245
vccbram_total_current=0.000245 vccbram_voltage=1.000000 vccint_dynamic_current=0.001494 vccint_static_current=0.014994
vccint_total_current=0.016489 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.002317 vcco33_static_current=0.004000
vcco33_total_current=0.006317 vcco33_voltage=3.300000 version=2017.2.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=96 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=24 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=12 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=6 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=240 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=270 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=135 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 carry4_functional_category=CarryLogic carry4_used=24
fdce_functional_category=Flop & Latch fdce_used=104 fdpe_functional_category=Flop & Latch fdpe_used=1
ibuf_functional_category=IO ibuf_used=5 lut1_functional_category=LUT lut1_used=2
lut2_functional_category=LUT lut2_used=10 lut3_functional_category=LUT lut3_used=51
lut4_functional_category=LUT lut4_used=5 lut5_functional_category=LUT lut5_used=6
obuf_functional_category=IO obuf_used=32
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=63400 lut_as_logic_fixed=0 lut_as_logic_used=65 lut_as_logic_util_percentage=0.10
lut_as_memory_available=19000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=105 register_as_flip_flop_util_percentage=0.08
register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=63400 slice_luts_fixed=0 slice_luts_used=65 slice_luts_util_percentage=0.10
slice_registers_available=126800 slice_registers_fixed=0 slice_registers_used=105 slice_registers_util_percentage=0.08
fully_used_lut_ff_pairs_fixed=0.08 fully_used_lut_ff_pairs_used=4 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=63400 lut_as_logic_fixed=0 lut_as_logic_used=65 lut_as_logic_util_percentage=0.10
lut_as_memory_available=19000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=54
lut_ff_pairs_with_one_unused_lut_output_fixed=54 lut_ff_pairs_with_one_unused_lut_output_used=53 lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=61 lut_flip_flop_pairs_util_percentage=0.10 slice_available=15850 slice_fixed=0
slice_used=31 slice_util_percentage=0.20 slicel_fixed=0 slicel_used=23
slicem_fixed=0 slicem_used=8 unique_control_sets_used=4 using_o5_and_o6_fixed=4
using_o5_and_o6_used=9 using_o5_output_only_fixed=9 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=56
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=147460 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=4
dsp=0 effort=2 estimated_expansions=90474 ff=105
global_clocks=1 high_fanout_nets=0 iob=37 lut=68
movable_instances=247 nets=336 pins=1338 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a100tcsg324-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=TOP -verilog_define=default::[not_specified]
usage
elapsed=00:00:35s hls_ip=0 memory_gain=435.250MB memory_peak=673.656MB