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**   ____  ____ 
**  /   /\/   / 
** /___/  \  /   Vendor: Xilinx 
** \   \   \/    
**  \   \        Readme Version: 1.3
**  /   /          
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** \   \  /  \   Associated Filename: 7 Series FPGA AMS Targeted Reference Design 
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** 
**  Device: XC7K325T
**  Purpose: Targeted Reference Design
** 
**     
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1.  REQUIREMENTS
    ------------ 
    a. Hardware
      i.  AC701 Evaluation Board 
      ii. AMS Daughter card
      iii.Mouse
      iv. External Signal Generator (optional)

    b. Software
      i. Vivado Design Suite 2013.3 (Logic or System or Embedded Edition)
     ii. National Instruments Software for GUI
	   i. RunTime engine - http://ftp.ni.com/support/softlib/labview/labview_development_system/2011/f2 patch/LVRTE2011std.exe		
	   ii. Drivers - NI-VISA v5.03 - http://joule.ni.com/nidu/cds/view/p/id/2251/lang/en  
        
2. DIRECTORY STRUCTURE 
   -------------------

    xadc_eval_design_ac701_v1_3 : Main TRD folder
    |
    |--hardware : Design files and scripts for implementation
    |  |
    |  |
    |  |---sources  : Hardware Design Folder
    |  |
    |  |   
    |  |---vivado  : Vivado project folder
    |      |   
    |      |---scripts  : Scripts to run the design
    |     
    |---software :  Software Design Folder
    |      |
    |      |----SDK_Export : Design exported from the bit file
    |      |
    |      |----xadc_eval_design : Contains the application source code
    |      |
    |      |----xadc_eval_design_bsp: Contains the board support package for AC701
    |      |
    |      |----xadc_eval_design_ac701 : Contains the generated bit files
    |
    |--ready_to_test : Contains the download.bit file which can be downloaded directly using Vivado to program the FPGA
    |
    |---doc  : Documentation folder
    |   |
    |   |--readme.txt : the file you are currently reading  
    |   |--ams101-ac701-doc-advisory.pdf : AMS101 AC701 Advisory Document  


3. SYSTEM GENERATION
   ------------------
   Opening the project with Vivado
      a. Navigate to xadc_eval_design_ac701/hardware/vivado/scripts folder 
      b. On the terminal run "vivado -source xadc_eval_design_gui.tcl" 
   
   This generates the Vivado system.

4. IMPLEMENTATION FLOW 
   -------------------
   a. In Vivado, click on `Generate Bitstream` in `Program and Debug` section of `Project Manager` tab.
   b. Click on `Yes` on being prompted to launch synthesis and implementation
   c. This will start the synthesis and implementation process and will result in the generation of bitstream
   d. Once the bit stream generation is complete click on `Open Implemented Design` in `Implementation` section of `Project Manager` tab.
   e. Then click on `Export Hardware for SDK` in `Export` option in the `File` menu.
   f. In the next dialogue box that is prompted, check the `Include Bitstream` and `Export Hardware` options only and click on `Ok`.
   
   This will create `SDK_Export` folder in `xadc_eval_design_ac701.sdk/SDK` folder.

5. RECREATING SOFTWARE PROJECT
   ---------------
   a. Copy the AMS TRD design zip file in the user PC. Unzip the design file.
   b. Copy SDK_Export from the xadc_eval_design_ac701.sdk area in vivado/runs folder to a folder of where SDK project needs to be created.
   c. Open Xilinx SDK from Windows environment by clicking on Start->All Programs->Xilinx Design Tools->SDK 14.5 -> Xilinx Software Development Kit. Select work space as the location where the SDK_Export design is copied.
   d. Click on File-> New -> Application Project as shown below
   e. Select Create New on Hardware Platform as shown below
   f. Create New Hardware Project. Browse for Target Hardware Specification
   g. Select system.xml from the SDK_Export/hw area as shown below.
   h. Click on Finish
   i. Create Application Project. Click on Next. 
   j. Select Empty Application. Click on Finish
   k. Copy the xadc_eval_design/src files from the unzipped TRD folder into the newly created project area. Xilinx SDK will automatically compile the files
   l. Right click on xadc_eval_design. Select C/C++ Build Settings as shown below.
   m. Click on Manage Configurations and select Release. Click on Set Active.
   n. Select Release as Configuration as shown below.
   o. Select xadc_eval_design->src and right click to select Refresh as shown below.

6. TESTING
`   -------
   a. Open Vivado Programming tool->Open HW session-> run through the wizard to program the FPGA with 'xadc_eval_design_ac701_v1_3/ready_to_test/xadc_eval_design.bit'
   b. Get the COM port for USB-UART bridge from 'Device Manager'.
   c. Download the AMS101 V1.1 gui installer from www.xilinx.com and istall it.
   d. Run the GUI after installing it.
   e. Connect GUI to hardware by selecting the COM port and clicking on Connect button.
   
7. KNOWN RESTRICTIONS
   ------------------
   The TRD has been tested with Xilinx SDK version 14.5.  


8. ADDITIONAL INFORMATION
   ----------------------
  Download the LabView runtime engine from http://ftp.ni.com/support/softlib/labview/labview_development_system/2011/f2 patch/LVRTE2011std.exe
