/*******************************************************************************
 ** � Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
 ** This file contains confidential and proprietary information of Xilinx, Inc. and
 ** is protected under U.S. and international copyright and other intellectual property laws.
 *******************************************************************************
 **   ____  ____
 **  /   /\/   /
 ** /___/  \  /   Vendor: Xilinx
 ** \   \   \/
 **  \   \
**  /   /
 ** /___/    \
** \   \  /  \   7 Series FPGA AMS Targeted Reference Design
 **  \___\/\___\
**
 **  Device: xc7a200t
 **  Version: 1.2
 **  Reference:
 **
 *******************************************************************************
 **
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 **
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 *******************************************************************************/

	//- Hex equivalents of ASCII characters
#define DESIGN_VERSION_REG	0x00
#define RAW_DATA_REG		0x01		//- Raw data collection
#define HIST_DATA_REG		0x02		//- Histogram data collection
#define DAC_B_OFFSET_REG 	0x14		//- Offset value for DAC-B
#define DAC_A_OFFSET_REG 	0x15		//- Offset value for VN DAC-A
#define DAC_RAMP_REG 	    0x16		//- Which DAC to ramp (A/B)
#define DAC_SINE_REG        0x17        //- Which DAC to use for sine wave (A/B)
#define SINE_ADRS_REG		0x04		//- Sine signal generation from DAC
#define SENSOR_DATA_REG		0x05		//- Sensor data collection
#define VREFN_DATA_REG		0x06		//- Short or VREFN data collection

#define CLK_SEL_REG			0x07		//- Clock divider - 6d
#define CHAN_SEL_REG		0x08		//- Channel option - 7d
#define IN_TYPE_REG			0x09		//- Input mode 8d

#define DEC_FACTOR_REG		0x0A		//- Decimation factor programming

#define ASCII_ZERO			0x30
#define SENSOR_OFFSET_1		0x34
#define SENSOR_OFFSET_2		0x35
