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\section{Dynamic power - tapered buffers for clock tree}
Task parameters:
\begin{itemize}
    \item \( f\textsubscript{clk} = 500\text{MHz} \)
    \item \( V\textsubscript{DD} = 1.2V \)
    \item \( \alpha\textsubscript{clk} = 1 \)
    \item \( C\textsubscript{H-tree} = 20.536pF = 57044C\)
    \item \( C = 0.36\si{\femto\farad} \), the input capacitance of an X1 inverter in the 65$\mu m$ process.
\end{itemize}
\rule{\textwidth}{0.5pt}
\textbf{a) }\newline
\( P\textsubscript{dyn} = \alpha\textsubscript{clk} \cdot f\textsubscript{clk} \cdot C \cdot V\textsubscript{DD}^2 = 1\cdot 500\text{MHz} \cdot 20.536pF \cdot 1.2V^2 \) = 14.8mW.

\bigbreak\noindent
\textbf{b)}\newline
The tapered buffer designed in \textit{lab 4} had the following characteristics 
\begin{itemize}
    \item N = 6
    \item F = 4.92
\end{itemize}
The total capacitance of the tapered buffer is thus the sum of the input and output capacitances scaled by F cumulatively for each consecutive inverter, starting with X4
\begin{equation*}
    C\textsubscript{taper} = \sum_{i=0}^{5}2 \cdot 4C \cdot 4.92^i = 29069C = 10.5pF
\end{equation*}
\( P\textsubscript{dyn} =  1 \cdot 500\text{MHz} \cdot 10.5pF \cdot 1.2V^2 \) = 7.5mW.

\bigbreak\noindent
\textbf{c)}\newline
The 10 stage tapered buffer has the following characteristics
\begin{itemize}
    \item N = 10
    \item F = 2.61
\end{itemize}
The total capacitance in the tapered buffer is, using the same reasoning as in 1b)
\begin{equation*}
    C\textsubscript{taper} = \sum_{i=0}^{9}2 \cdot 4C \cdot 2.61^i = 72885.2C = 26.2pF
\end{equation*}
\( P\textsubscript{dyn} =  1 \cdot 500\text{MHz} \cdot 26.2pF \cdot 1.2V^2 \) = 18.9mW.

In this configuration the tapered buffer has a \textit{path delay} of
\( D = 10\cdot 2.61 + 10 = 36.1 \), or 180.5ps in absolute terms (with $\tau = 5ps$).

\bigbreak\noindent
\textbf{d)}
The width of the unit nMOS transistor is 0.1$\mu m$ in the 65$\mu m$ process. The width of the unit pMOS is double that. Therefore, simplified, the total width of an X1 inverter is 0.3$\mu m$ while the channel length is constantly 0.06$\mu m$. Thus, for a single stage i in the tapered buffer, the area is \( W L X \), where X is the scale relative to the unit inverter. Since the smallest inverter is X4 and the scaling factor is F, the scale \( X = 4\cdot F^i\).

The area of the 6-stage buffer is 
\[ A\tss{6-stage} = WL\sum_\tss{i=0}^5 4\cdot 4.92^i =  261 \mu m^2\]
whereas the area of the 10-stage buffer is
\[ A\tss{10-stage} = WL\sum_\tss{i=0}^{9} 4\cdot 2.61^i =  656 \mu m^2\]


\clearpage
\textbf{e)}
The results of this exercise are summarised in table \ref{tab:1}. From this we can surmise that, due to the insensitivity of the delay to number of stages, a significant increase in the number of stages gives a minuscule increase in delay from the optimum value. There is, however, a large area and power penalty, as each extra stage is exponentially bigger, taking more power to switch. As a final note, the dynamic power of the tapered buffer is far larger than that of the load itself, unsurprisingly, as the final inverter of the tapered buffer alone has a diffusion capacitance comparable to that of the load in magnitude.

\begin{table}[h]
\centering
\caption{\textit{Summarised results for task 1.}}
\label{tab:1}
\begin{tabular}{|l|c|c|c|} 
\hline
                                                                                      & \multicolumn{1}{l|}{\begin{tabular}[c]{@{}l@{}}My own tapered \\buffer from lab 4 \end{tabular}} & \multicolumn{1}{l|}{\begin{tabular}[c]{@{}l@{}}A 10-stage tapered \\buffer with F = 2.61 \end{tabular}} & \multicolumn{1}{l|}{\begin{tabular}[c]{@{}l@{}}The load capacitances \\themselves \end{tabular}}  \\ 
\hline
Delay                                                                                 & 177ps                                                                                            & 180ps                                                                                                   & n/a                                                                                               \\ 
\hline
Dynamic Power                                                                         & 7.5mW                                                                                           & 18.9mW                                                                                                  & 14.8mW                                                                                            \\ 
\hline
\begin{tabular}[c]{@{}l@{}}Tapered buffer area \\(only transistor area) \end{tabular} & 262$\mu m^2$                                                                                    & 656$\mu m^2$                                                                                           & n/a                                                                                               \\
\hline
\end{tabular}
\end{table}

%\clearpage
\section{Dynamic power - activity factors}
Since the \textit{AOI21} and \textit{OAI21} gates are really just cascaded two-input gates with an output inverter, with switching probabilities P given by table 5.1 (W\&H), P and $\alpha$ can be worked out successively, from input to output. This has been done for the aforementioned compound gates with the results in figures \ref{fig:AOI21} and \ref{fig:OAI21}, respectively.
\begin{figure}[h]
    \centering
    \includegraphics[width=0.5\linewidth]{figures/handin2_2_AOI21.pdf}
    \caption{\textit{AOI21 Gate}}
    \label{fig:AOI21}
\end{figure}

\begin{figure}[h]
    \centering
    \includegraphics[width=0.5\linewidth]{figures/handin2_2_OAI21.pdf}
    \caption{\textit{OAI21 Gate}}
    \label{fig:OAI21}
\end{figure}

\clearpage
\section{Static power - power gating} 
\textbf{a)}
%\[ I_D\textsubscript{sat} = \frac{k}{2}\cdot V\textsubscript{GT}^2 = \frac{k}{2}\cdot (V\textsubscript{GS}-V_T)^2 \]
The normalised delay of a circuit depends on the capacitive load it presents and its effective resistance
\[ d = 0.7 C  R\tss{eff} \] where $ R\tss{eff} = \frac{V\tss{DD}}{I\tss{ON}} $. V\tss{DD} and I\tss{ON} are known to be 1.2V and 100mA respectively and therefore R\tss{eff} = $\SI{12}{\ohm}$. 
%In the context of a switch, we can assume that \( I\tss{ON} = I\tss{D\tss{sat}} \) and \( V\tss{GS} = V\tss{DD} \), therefore  \[ R\tss{eff} = \frac{V\tss{DD}}{\frac{k}{2}(V\tss{DD}-V_T)^2}\] 
In order for the delay of the combinational logic to increase by a maximum of 2\%, the header switch must contribute at most 2\% to the overall R\tss{eff} of the circuit. This corresponds to \[ R\tss{eff\tss{header}} \leq 2\%\frac{V\tss{DD}}{I\tss{ON}} = 2\% \cdot 12\Omega = 0.24\Omega\]   
Since the pMOS used in the header switch has an effective resistance of $\SI{2.5}{\kilo\ohm\micro\meter}$, the width required to fulfill the above criteria is \[ W \geq \frac{R\tss{eff\tss{pMOS}}}{R\tss{eff\tss{header}}} = \frac{\SI{2.5}{\kilo\ohm\micro\meter}}{0.24\Omega} = 10416\mu m \]


\bigbreak\noindent\textbf{b)}\newline 
In \textit{lab 1} it was determined that the gate capacitance \( C_G\) of a unit transistor (\( W = 0.1\mu m\)) is \( \SI{0.12}{\femto\farad} \). The capacitance of the header switch can therefore be calculated \[ C = \SI{1.2}{\femto\farad\per\micro\meter\squared} \cdot W \si{\micro\meter} = 12.5pF\]

\bigbreak\noindent\textbf{c)}\newline 
The energy required to use the switch is \[ E = \frac{1}{2}\cdot C \cdot V\tss{DD}^2 = 9pJ \]

\clearpage
\section{Ripple carry cell reconsidered}
\textbf{a)}  
\begin{align*}
    G =& A \cdot B\\ P =& A \oplus B
\end{align*} 

\bigbreak\noindent 
\textbf{b)} 
\begin{align*}
    C\textsubscript{out} =& G+P\cdot C\textsubscript{in}\\
    S =& P \oplus C\textsubscript{in}
\end{align*}

\bigbreak\noindent
\textbf{c)}\newline
In the same way as in prelab 2, only the inverted \textit{carry function} can be realized in a single CMOS gate (using exclusively positive inputs). This gives us \( f(P, G, C\tss{in}) = \overline{f\tss{maj}} = \overline{G+P\cdot C\tss{in}} \). Thus, for the n-net \[f_n=C\tss{out} = G+P\cdot C\tss{in}\] and just as before, the p-net then can be defined as the \textit{dual} of the n-net\[f_p = f_n^D = G \cdot (P+C\tss{in})\] The final transistor schematic (with output inverter) is shown below in figure \ref{fig:pg_maj}.

\begin{figure}[h]
    \centering
    \includegraphics[width=0.5\linewidth]{figures/PG_maj_func.pdf}
    \caption{\textit{Transistor-level carry cell using propagate and generate signals.}}
    \label{fig:pg_maj}
\end{figure}

\bigbreak\noindent
\textbf{d)}\newline
The \textit{logical effort} g of the carry cell is the input capacitance of the gate relative to the input capacitance of an inverter that can drive the same amount of current.
\[ g\tss{C\tss{in}} = \frac{C\tss{in}}{C\tss{inv}} = \frac{2C+4C}{3C} = 2\]
The \textit{parasitic delay} p is the capacitance directly connected to the output of the gate relative to that of the unit inverter, that is 4C from the p-net and 3C from the n-net
\[ p = \frac{4C+1C+2C}{3C} = \frac{7}{3} \]
It is worth noting that only p has changed in this reconsidered design. In other words, the \textit{gate complexity} has stayed the same as far as C\tss{in} is concerned.

\bigbreak\noindent
\textbf{e)}\newline
In order to determine the relative size of the output inverter that will result in minimum delay, we have to find the optimal \textit{stage effort} $\hat{f} = F^\frac{1}{N}$. The delay is then simply \[ D\tss{min} = \sum d_i = D_F+P = \sum \hat{f_i}+P \]
where $D_F$ is the \textit{path effort delay} and P is the \textit{path parasitic delay}.

The \textit{logical efforts} of the carry cell and inverter are fixed (g only describes the relative complexity of the gate itself) as well as their respective parasitic delays. Thus it is the input capacitance of the inverter that must be changed.

First, we derive the various \textit{path efforts} (under the assumption that the output drives an identical carry cell)
\begin{align*}
    G =& g\tss{carry} \cdot g\tss{inv} = 2\cdot 1 = 2 \\ 
    B =& 1 \\
    H =& \frac{C\tss{out}(path)}{C\tss{in}(path)} = \frac{6C}{6C} = 1
\end{align*}
The \textit{path effort} F is therefore \[ F = GBH = 2 \] giving an optimal \textit{stage delay} of \( \hat{f} = F^\frac{1}{N} = \sqrt{2} \), where N is the number of stages, two in this case.

Now that $\hat{f}$ is known, the input capacitance of the inverter can be calculated using the \textit{capacitance transformation formula}
\[ C\tss{in\tss{i}} = \frac{C\tss{out\tss{i}}\cdot g_i}{\hat{f_i}} \Rightarrow \frac{6C \cdot 1}{\sqrt{2}} = 3\sqrt{2}C \]
again, assuming the output is driving an identical carry cell.

The inverter size relative to the carry gate $C\tss{in}$ (or equivalently, the \textit{electrical effort} $h\tss{carry}$) is thus \( \frac{3\sqrt{2}C}{6C} = 0.707 \)

\bigbreak\noindent\textbf{f)}\newline
The resulting normalized delay of a 16-bit ripple-carry chain can be computed directly
\begin{align*}
    D = N\hat{f}+P =& 16\cdot 2 \cdot \sqrt{2} + 16\cdot (\frac{7}{3} + 1)p\tss{inv}\\
    =& 32\sqrt{2}+\frac{160}{3}p\tss{inv} \xrightarrow{p\tss{inv}\approx1} 98.6\tau \\
    =&  492.9ps
\end{align*} 
with each link having $6.2\tau$ vs. the $9.5\tau$ of prelab 2; a 35\% improvement!

\clearpage
\section{The Dot operator or PG logic}
\bigbreak\textbf{a)}\newline
The generic block propagate can be expressed as 
\begin{equation*}
    P\tss{i:j} = P\tss{i:k}P\tss{k-1:j}
\end{equation*}
In this case we have two consecutive bits and hence the expression becomes reduced to
\begin{equation*}
    P\tss{i+1:i} = P\tss{i+1}P\tss{i}
\end{equation*}

\bigbreak\noindent\textbf{b)}\newline
Likewise, the generic block generate is
\[ G\tss{i:j} = G\tss{i:k}+P\tss{i:k}G\tss{k-1:j} \]
which is in this case reduced to 
\[ G\tss{i:j} = G\tss{i+1} + P\tss{i+1}G\tss{i} \]

\bigbreak\noindent\textbf{c)}\newline
The expression for the \textit{generate} in task \textbf{5b)} is the same as the \textit{carry function} in task \textbf{4c)}. This is no coincidence, as one can redefine $C\tss{in}$ as the initial \textit{generate}, $G\tss{0:0}$, to derive the same expression. Thus the schematic will remain unchanged, but with slightly different inputs, as shown in figure \ref{fig:PG_maj_func_generic}.

\begin{wrapfigure}{l}{0.5\textwidth}
    %\centering
    \includegraphics[width=0.48\textwidth]{figures/PG_maj_func_generic.pdf}
    \caption{\textit{Transistor-level block generate gate. p-net, n-net and output inverter highlighted.}}
    \label{fig:PG_maj_func_generic}
\end{wrapfigure}

\bigbreak\noindent\textbf{d)}\newline
Using the generic expressions from \textbf{4a)} and \textbf{b)}, the \textit{generate} and \textit{propagate} for the pairwise signals are
\begin{align*}
    P\tss{i+3:i} =& P\tss{i+3:i+2}\cdot P\tss{i+1:i} \\
    G\tss{i+3:i} =& G\tss{i+3:i+2} + P\tss{i+3:i+2}\cdot G\tss{i+1:i}
\end{align*}


\clearpage
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