m255
K4
z2
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
dE:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1
Edots
Z0 w1542651241
Z1 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
Z2 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1
Z3 dE:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky
Z4 8E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/DOTs.vhd
Z5 FE:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/DOTs.vhd
l0
L4
VOmi=izTK<@335:o5NU3]X1
!s100 ?Z_n[0k2>GNA=24<kH5GO2
Z6 OV;C;10.5b;63
32
Z7 !s110 1542676562
!i10b 1
Z8 !s108 1542676562.000000
Z9 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/DOTs.vhd|
Z10 !s107 E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/DOTs.vhd|
!i113 1
Z11 o-work work -2002 -explicit
Z12 tExplicit 1 CvgOpt 0
Aarch
R1
R2
DEx4 work 4 dots 0 22 Omi=izTK<@335:o5NU3]X1
l16
L14
V3b3AHfKj>YHHoSjA49X]_0
!s100 Y=RbSB:KI7i>NF_d4:1T52
R6
32
R7
!i10b 1
R8
R9
R10
!i113 1
R11
R12
Ee
Z13 w1542651240
R1
R2
R3
Z14 8E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/E.vhd
Z15 FE:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/E.vhd
l0
L4
Vz9RbdOBc7;DK74>Gj`EBF0
!s100 >zVSEl4LR5_192<4b;Z]_0
R6
32
R7
!i10b 1
R8
Z16 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/E.vhd|
Z17 !s107 E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/E.vhd|
!i113 1
R11
R12
Aarch
R1
R2
DEx4 work 1 e 0 22 z9RbdOBc7;DK74>Gj`EBF0
l13
L11
V>=a?D?ggjH=adCk;J0^5W3
!s100 :?QP6zMQ:1fcJ2G^a8Jkd1
R6
32
R7
!i10b 1
R8
R16
R17
!i113 1
R11
R12
Egdot
Z18 w1542651242
R1
R2
R3
Z19 8E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Gdot.vhd
Z20 FE:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Gdot.vhd
l0
L4
VEJ<T1nh0c4k:59G^W;^e12
!s100 2dCad?2Pl4C1Dl]9lYEi[1
R6
32
R7
!i10b 1
R8
Z21 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Gdot.vhd|
Z22 !s107 E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Gdot.vhd|
!i113 1
R11
R12
Aarch
R1
R2
DEx4 work 4 gdot 0 22 EJ<T1nh0c4k:59G^W;^e12
l14
L12
VbmIghKA5EPRcZ:70TaeCT1
!s100 nYSA:PKBf5P2Uk_ZaPLC>3
R6
32
R7
!i10b 1
R8
R21
R22
!i113 1
R11
R12
Einit
R13
R1
R2
R3
Z23 8E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Init.vhd
Z24 FE:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Init.vhd
l0
L4
Vljck`;@cYFKM390zWdKD^3
!s100 @HceLd6F]fAR<VbN?N4T21
R6
32
R7
!i10b 1
R8
Z25 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Init.vhd|
Z26 !s107 E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Init.vhd|
!i113 1
R11
R12
Aarch
R1
R2
DEx4 work 4 init 0 22 ljck`;@cYFKM390zWdKD^3
l14
L12
VOe:`02c<fKGBko0d?7;R:0
!s100 13<CZ_`jm?bNXn;FFiO=S2
R6
32
R7
!i10b 1
R8
R25
R26
!i113 1
R11
R12
Einitcarry
Z27 w1542651238
R1
R2
R3
Z28 8E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/InitCarry.vhd
Z29 FE:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/InitCarry.vhd
l0
L4
VPN4jeOR]0kiDI:V>SVfnE1
!s100 h0E4OJkfoD4UjoiTPJNkW1
R6
32
R7
!i10b 1
R8
Z30 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/InitCarry.vhd|
Z31 !s107 E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/InitCarry.vhd|
!i113 1
R11
R12
Aarch
R1
R2
DEx4 work 9 initcarry 0 22 PN4jeOR]0kiDI:V>SVfnE1
l15
L13
V9RbGTbecQe1klR0ESenTZ3
!s100 KlhcZWhe@LQPoQ;:Z4GbF0
R6
32
R7
!i10b 1
R8
R30
R31
!i113 1
R11
R12
Ppkg_tb_alu
R2
R1
Z32 w1542680683
R3
Z33 8E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/initial_ALU_code.vhdl
Z34 FE:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/initial_ALU_code.vhdl
l0
L7
V_6_5[>NOZG]7fE7YPcD?Z2
!s100 7NH^ej^SQZ5Ak5`<Xo0c51
R6
32
b1
Z35 !s110 1542680687
!i10b 1
Z36 !s108 1542680687.000000
Z37 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/initial_ALU_code.vhdl|
Z38 !s107 E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/initial_ALU_code.vhdl|
!i113 1
R11
R12
Bbody
DPx4 work 10 pkg_tb_alu 0 22 _6_5[>NOZG]7fE7YPcD?Z2
R2
R1
l0
L23
VWS^NGT^<XQKgC1_[G[Ui^1
!s100 >M?TRFio=Yhb1H?PFjT=g3
R6
32
R35
!i10b 1
R36
R37
R38
!i113 1
R11
R12
Esklansky
R18
Z39 DPx4 ieee 9 math_real 0 22 Sk6CSihbPL<f[^Shm]=KX0
Z40 DPx4 ieee 11 numeric_std 0 22 :ASDNFgHXf_ih3J@9F3Ze1
R1
R2
R3
Z41 8E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Sklansky.vhd
Z42 FE:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Sklansky.vhd
l0
L6
Vd3]6z6hzfEJTQTUX8_UZ10
!s100 `e<U`DTXcVTh`b?fcBHi?2
R6
32
Z43 !s110 1542676563
!i10b 1
R8
Z44 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Sklansky.vhd|
Z45 !s107 E:/sync/program_files/ModelSim/DAT110_Methods_for_Electronic_System_Design_and_Verification_HT18/lab1/sklansky/Sklansky.vhd|
!i113 1
R11
R12
Artl
R39
R40
R1
R2
DEx4 work 8 sklansky 0 22 d3]6z6hzfEJTQTUX8_UZ10
l70
L17
VWPVREA4DI>9X[ACU6G9[E1
!s100 Rj@Ib?iI^8H:9GbQ[gOgm3
R6
32
R43
!i10b 1
R8
R44
R45
!i113 1
R11
R12
