Lecture on Labs 4-6
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ADC | MCP3202
DAC | MCP4822

2 channels in/out of ADC/DAC.

3 clocks in system
- system clock 100MHz
- Serial SPI clock ?MHz   (1MHz i think, check datasheet)
- Sampling clock 40 MHz


Off-board -> send lower frequency clock (50% duty).
Internally -> use 'clock_enable' (single pulse at lower frequency).

See "Hints on clocking" for timings.

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AD/DA quantities

delta = Umax/2^N, where N is number of bits.

Logarithmic converter -> "compander".

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SPI
* Everything can be done on positive flank
  - Set SPI data on SPI_CLK pos flank one cycle beforehand -> easier than setting between pos flanks.
  
Pipeline: simultaneously read new val (from ADC) and send old val (to DAC).

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Interpolation (zero stuffing)
Decimation (sample skipping)


Start with highest interpolation, end with highest decimation.
- Preserves spectrum.

Divide multi-rate ratio into factors:
eg.  44,1 kHz => 48 kHz

     48/44,1 = 480/441 = 160/147
  -> (4 x 8 x 5)/(3 x 7 x 7)  
  
LP-filter between interpolaters and decimators.



In lab 
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40MHz -> 30MHz

30/40 = 3/4

Interpolate by 3 (insert two zeros per sample)
Decimate by 4 (skip 3 values per 4 samples)