Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (ISE) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) 5af97e322dff4a28ad01fcca8a7eb159.65D690A220B842349D8449A04E0DD83B.4 Target Package: csg324
Registration ID 210655449_178259189_210672038_863 Target Speed: -3
Date Generated 2018-02-28T10:42:48 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-4790 CPU @ 3.60GHz CPU Speed 3591 MHz
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-4790 CPU @ 3.60GHz CPU Speed 3591 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=1
  • 8-bit comparator equal=1
 FSMs=1 Multiplexers=17
  • 16-bit 2-to-1 multiplexer=9
  • 16-bit 5-to-1 multiplexer=1
  • 8-bit 2-to-1 multiplexer=6
  • 8-bit 3-to-1 multiplexer=1
 RAMs=3
  • 16x3-bit single-port distributed Read Only RAM=1
  • 256x12-bit single-port distributed RAM=1
  • 256x8-bit single-port distributed RAM=1
 Registers=48
  • Flip-Flops=48
 Xors=12
  • 1-bit xor2=8
  • 8-bit xor2=4
 		MiscellaneousStatistics
  • AGG_BONDED_IO=86
  • AGG_IO=86
  • AGG_SLICE=56
  • NUM_BONDED_IOB=86
  • NUM_BSFULL=53
  • NUM_BSLUTONLY=144
  • NUM_BSREGONLY=6
  • NUM_BSUSED=203
  • NUM_BUFG=1
  • NUM_LOGIC_O5ANDO6=15
  • NUM_LOGIC_O6ONLY=102
  • NUM_LUT_RT_O5=2
  • NUM_SLICEL=2
  • NUM_SLICEM=20
  • NUM_SLICEX=34
  • NUM_SLICE_CONTROLSET=9
  • NUM_SLICE_CYINIT=214
  • NUM_SLICE_F7MUX=42
  • NUM_SLICE_F8MUX=20
  • NUM_SLICE_FF=63
  • NUM_SLICE_UNUSEDCTRL=15
  • NUM_SPRAM_O6ONLY=80
  • NUM_UNUSABLE_FF_BELS=9
 		NetStatistics
  • NumNets_Active=271
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=39
  • NumNodesOfType_Active_BOUNCEIN=56
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=1
  • NumNodesOfType_Active_CLKPIN=41
  • NumNodesOfType_Active_CLKPINFEED=1
  • NumNodesOfType_Active_CNTRLPIN=71
  • NumNodesOfType_Active_DOUBLE=621
  • NumNodesOfType_Active_GENERIC=96
  • NumNodesOfType_Active_GLOBAL=15
  • NumNodesOfType_Active_INPUT=9
  • NumNodesOfType_Active_IOBIN2OUT=85
  • NumNodesOfType_Active_IOBOUTPUT=85
  • NumNodesOfType_Active_LUTINPUT=1102
  • NumNodesOfType_Active_OUTBOUND=199
  • NumNodesOfType_Active_OUTPUT=185
  • NumNodesOfType_Active_PADINPUT=75
  • NumNodesOfType_Active_PADOUTPUT=11
  • NumNodesOfType_Active_PINBOUNCE=287
  • NumNodesOfType_Active_PINFEED=1256
  • NumNodesOfType_Active_QUAD=827
  • NumNodesOfType_Active_REGINPUT=90
  • NumNodesOfType_Active_SINGLE=844
  • NumNodesOfType_Gnd_BOUNCEIN=20
  • NumNodesOfType_Gnd_CNTRLPIN=4
  • NumNodesOfType_Gnd_HGNDOUT=12
  • NumNodesOfType_Gnd_INPUT=8
  • NumNodesOfType_Gnd_PINBOUNCE=24
  • NumNodesOfType_Gnd_REGINPUT=12
  • NumNodesOfType_Vcc_HVCCOUT=11
  • NumNodesOfType_Vcc_LUTINPUT=17
  • NumNodesOfType_Vcc_PINFEED=17
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=45
  • IOB-IOBS=41
  • SLICEL-SLICEM=1
  • SLICEX-SLICEL=9
  • SLICEX-SLICEM=5
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • FF_SR=6
  • INVERTER=1
  • IOB=86
  • IOB_IMUX=11
  • IOB_INBUF=11
  • IOB_OUTBUF=75
  • LUT5=17
  • LUT6=117
  • LUT_OR_MEM6=80
  • PAD=86
  • REG_SR=57
  • SELMUX2_1=62
  • SLICEL=2
  • SLICEM=20
  • SLICEX=34
 
Configuration Data
FF_SR
  • CK=[CK:6] [CK_INV:0]
  • SRINIT=[SRINIT0:6]
  • SYNC_ATTR=[ASYNC:6]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:75]
  • SLEW=[SLOW:75]
  • SUSPEND=[3STATE:75]
 LUT_OR_MEM6
  • CLK=[CLK:80] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:80]
  • RAMMODE=[SPRAM64:80]
 REG_SR
  • CK=[CK:57] [CK_INV:0]
  • LATCH_OR_FF=[FF:57]
  • SRINIT=[SRINIT0:56] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:57]
 SLICEL
  • CLK=[CLK:2] [CLK_INV:0]
 SLICEM
  • CLK=[CLK:20] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:19] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 FF_SR
  • CE=4
  • CK=6
  • D=6
  • Q=6
  • SR=6
 INVERTER
  • IN=1
  • OUT=1
 IOB
  • I=11
  • O=75
  • PAD=86
 IOB_IMUX
  • I=10
  • I_B=1
  • OUT=11
 IOB_INBUF
  • OUT=11
  • PAD=11
 IOB_OUTBUF
  • IN=75
  • OUT=75
 LUT5
  • A1=12
  • A2=16
  • A3=14
  • A4=7
  • A5=8
  • O5=17
 LUT6
  • A1=63
  • A2=94
  • A3=110
  • A4=116
  • A5=117
  • A6=117
  • O6=117
 LUT_OR_MEM6
  • A1=80
  • A2=80
  • A3=80
  • A4=80
  • A5=80
  • A6=80
  • CLK=80
  • DI1=80
  • O6=80
  • WA1=80
  • WA2=80
  • WA3=80
  • WA4=80
  • WA5=80
  • WA6=80
  • WA7=80
  • WA8=80
  • WE=80
 PAD
  • PAD=86
 REG_SR
  • CE=54
  • CK=57
  • D=57
  • Q=57
  • SR=57
 SELMUX2_1
  • 0=62
  • 1=62
  • OUT=62
  • S0=62
 SLICEL
  • A=1
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • AQ=2
  • AX=1
  • B=2
  • B1=1
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • C1=1
  • C2=2
  • C3=2
  • C4=2
  • C5=2
  • C6=2
  • CE=2
  • CLK=2
  • CMUX=1
  • CQ=1
  • CX=2
  • D1=2
  • D2=2
  • D3=2
  • D4=2
  • D5=2
  • D6=2
  • SR=2
 SLICEM
  • A1=20
  • A2=20
  • A3=20
  • A4=20
  • A5=20
  • A6=20
  • AX=20
  • B1=20
  • B2=20
  • B3=20
  • B4=20
  • B5=20
  • B6=20
  • BMUX=4
  • BQ=16
  • BX=20
  • C1=20
  • C2=20
  • C3=20
  • C4=20
  • C5=20
  • C6=20
  • CE=20
  • CLK=20
  • CX=20
  • D1=20
  • D2=20
  • D3=20
  • D4=20
  • D5=20
  • D6=20
  • DX=20
  • SR=16
  • WE=16
 SLICEX
  • A=26
  • A1=14
  • A2=25
  • A3=29
  • A4=30
  • A5=30
  • A6=30
  • AMUX=5
  • AQ=11
  • AX=7
  • B=21
  • B1=20
  • B2=27
  • B3=27
  • B4=27
  • B5=27
  • B6=27
  • BMUX=5
  • BQ=11
  • BX=5
  • C=25
  • C1=14
  • C2=22
  • C3=25
  • C4=27
  • C5=28
  • C6=28
  • CE=16
  • CLK=19
  • CMUX=4
  • CQ=9
  • CX=5
  • D=19
  • D1=18
  • D2=22
  • D3=24
  • D4=24
  • D5=24
  • D6=24
  • DMUX=3
  • DQ=7
  • DX=2
  • SR=19
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt on -ol high -xe n -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 4 4 0 0 0 0 0
map 15 8 0 0 0 0 0
ngdbuild 11 11 0 0 0 0 0
par 8 8 0 0 0 0 0
trce 8 8 0 0 0 0 0
xst 18 18 0 0 0 0 0
 
Project Statistics
PROPEXT_MapGlobalOptimization_spartan6=Speed PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_MapLogicOptimization_spartan6=true PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthFsmEncode=One-Hot
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserBrowsedStrategyFiles=C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2018-02-28T08:28:43
PROP_intWbtProjectID=65D690A220B842349D8449A04E0DD83B PROP_intWbtProjectIteration=4
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xstReadCores=false
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_MapExtraEffort_spartan6=Normal PROP_xilxMapEnableMultiThreading=2
PROP_DevDevice=xc6slx16 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_parEnableMultiThreading_spartan6=4 PROP_DevSpeed=-3
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=13
 
Power Data
Customer
Customer=TBD Customer Class=TBD
Device
Family=Spartan6 Die=xc6slx16 Package=csg324 Speedgrade=-3
Tool Data
version=14.7 platform=win CPU=NA Peak Memory=514 MB
Tool= Num run=1
Power Settings
Temp grade=C-Grade Process=Typical Settings file=No Simulation file=None
Simu_net_matched=NA Netlist_net_matched=NA PCF file=Yes Pct_clock_constrained=100
Pct_inputs_defined=0 User_junc_temp=0.0 Ambient temp=25.0 User effective thetaJA=NA
Airflow=0 heatsink=None User ThetaSA=NA Board selection=Medium (10x10)
Board layers=8 to 11 User ThetaJB=NA User Board Temp=NA Junction temp=29.8
Num run=1
Tool Defaults
Input toggle=12.5 Output toggle=12.5 Output enable=100.0 Bi-dir toggle=12.5
Bidir output enable=100.0 Output load=5.0 FF toggle=12.5 ram enable=50.0
ram write=50.0 DSP output toggle=12.5 Set/Reset probability=1.0 Set/Reset toggle=1.0
Enable probability=99.0 Enable toggle=1.0
Power Results
On-chip power=174.21 Effective ThetaJA=27.8 ThetaSA=0.0 ThetaJB=13.7
Off-chip power=0.00
Thermal Power
Logic=2.93 Signal=6.20 Clock=4.73 BRAM=0.00
DSP=0.00 PLL=0.00 MMCM=0.00 Phaser=0.00
PCIE=0.00 IO=138.85 GTX=0.00 DevStatic=21.50
Supply Power
Vccint voltage=1.20 Vccint total current=19.85 Vccint static current=7.02 Vccint dynamic current=12.83
Vccaux voltage=2.50 Vccaux total current=6.07 Vccaux static current=3.23 Vccaux dynamic current=2.84
Vcco25 voltage=2.50 Vcco25 total current=54.08 Vcco25 static current=2.00 Vcco25 dynamic current=52.08
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=5 NGDBUILD_NUM_FDCE=54 NGDBUILD_NUM_FDP=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=10 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT2=4
NGDBUILD_NUM_LUT3=17 NGDBUILD_NUM_LUT4=9 NGDBUILD_NUM_LUT5=29 NGDBUILD_NUM_LUT6=91
NGDBUILD_NUM_MUXF7=4 NGDBUILD_NUM_OBUF=75 NGDBUILD_NUM_RAM256X1S=20
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=5 NGDBUILD_NUM_FDCE=54 NGDBUILD_NUM_FDP=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=10 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=1
NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_LUT3=17 NGDBUILD_NUM_LUT4=9 NGDBUILD_NUM_LUT5=29
NGDBUILD_NUM_LUT6=91 NGDBUILD_NUM_MUXF7=4 NGDBUILD_NUM_OBUF=75 NGDBUILD_NUM_RAM256X1S=20
NGDBUILD_NUM_TS_TIMESPEC=1
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=NO -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=One-Hot -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5